//      Release   : $State: $
//-----------------------------------------------------------------------------


`ifndef NO_ENABLE_TARMAC

`include "TraceAndCompare.sv"


`ifndef TNC_CPU
`define TNC_CPU


`ifdef EAGLE_OPCODE_COVERAGE//{
`include "xm_arm_opcode_coverage.sv"
`include "xm_thumb_opcode_coverage.sv"
`include "xm_arm_neon_opcode_coverage.sv"
`include "xm_thumb_neon_opcode_coverage.sv"
`include "xm_a64_opcode_coverage.sv"
`endif//}


module TnC_cpu (
		cpuid,
		clusterid_init,
		ck_gclkcr,
		cycle,
		reset,
		cp15sdisable,
		cfgte,
		vinithi,
		cfgend,
		iminln,
		periphbase,
		
		iss_mismatch,
		iss_fatal,
		iss_eot,
		
		ds_aes_restore_atag_0t1,
		ds_aes_restore_atag_1t1,
		ds_aes_restore_atag_2t1,
		ds_aes_restore_atag_3t1,
		ds_aes_restore_atag_4t1,
		ds_aes_restore_atag_5t1,
		ds_aes_restore_dw_0t1,
		ds_aes_restore_dw_1t1,
		ds_aes_restore_dw_2t1,
		ds_aes_restore_dw_3t1,
		ds_aes_restore_dw_4t1,
		ds_aes_restore_dw_5t1,
		ds_aes_restore_rtag_0t0_0u2,
		ds_aes_restore_rtag_1t0_1u2,
		ds_aes_restore_rtag_2t0_2u2,
		ds_aes_restore_rtag_3t0_3u2,
		ds_aes_restore_rtag_4t0_4u2,
		ds_aes_restore_rtag_5t0_5u2,
		ds_aes_restore_type_0t1,
		ds_aes_restore_type_1t1,
		ds_aes_restore_type_2t1,
		ds_aes_restore_type_3t1,
		ds_aes_restore_type_4t1,
		ds_aes_restore_type_5t1,
		ds_aes_restore_zbits_0t1,
		ds_aes_restore_zbits_1t1,
		ds_aes_restore_zbits_2t1,
		ds_aes_restore_zbits_3t1,
		ds_aes_restore_zbits_4t1,
		ds_aes_restore_zbits_5t1,
		ds_aes_retire_vld_0t0,
		ds_aes_retire_vld_1t0,
		ds_aes_retire_vld_2t0,
		ds_aes_retire_vld_3t0,
		ds_aes_retire_vld_4t0,
		ds_aes_retire_vld_5t0,
		
		arm_resq_ret_data_0t2_q,
		arm_resq_ret_data_1t2_q,
		arm_resq_ret_data_2t2_q,
		arm_resq_ret_data_3t2_q,
		arm_resq_ret_data_4t2_q,

		`ifdef MAIA
		arm_resq_ret_data_5t2_q,
		`endif

		ext_resq_ret_data_0t2_q,
		ext_resq_ret_data_1t2_q,
		ext_resq_ret_data_2t2_q,
		ext_resq_ret_data_3t2_q,
		ext_resq_ret_data_4t2_q,

		`ifdef MAIA
		ext_resq_ret_data_5t2_q,
		`endif

		ds_psr_restore_atag_0t0_0u2,
		ds_psr_restore_atag_1t0_1u2,
		ds_psr_restore_atag_2t0_2u2,
		ds_psr_restore_rtag_0t0_0u2,
		ds_psr_restore_rtag_1t0_1u2,
		ds_psr_restore_rtag_2t0_2u2,
		ds_psr_retire_vld_0t0,
		ds_psr_retire_vld_1t0,
		ds_psr_retire_vld_2t0,
		ds_psr_ret_data_0t2_q,
		ds_psr_ret_data_1t2_q,
		
		//D1: Opcode
		ifu_inst_h_0d1,
		ifu_inst_h_1d1,
		ifu_inst_h_2d1,
		ifu_inst_l_0d1,
		ifu_inst_l_1d1,
		ifu_inst_l_2d1,
		
		ifu_size_0d1,
		ifu_size_1d1,
		ifu_size_2d1,
		
		ifu_tbit_0d1,
		ifu_tbit_1d1,
		ifu_tbit_2d1,
		
		ifu_vld_0d1,
		ifu_vld_1d1,
		ifu_vld_2d1,
		
		ifu_pcalgn_abt_pend,
		
		dec_genq_1free,
		dec_genq_2free,
		dec_genq_3free,
		
		//R2: Fusion
		ok_uop_vld_0r2,
		inst_end_0r2,
		size_0r2,
		tbit_0r2,
		fused_parent_0r2,
		id_preamble_0r2,
		inst_opcode_0r2,
		dsu_dispq_1free,
		
		ok_uop_vld_1r2,
		inst_end_1r2,
		size_1r2,
		tbit_1r2,
		fused_parent_1r2,
		id_preamble_1r2,
		inst_opcode_1r2,
		dsu_dispq_2free,
		
		ok_uop_vld_2r2,
		inst_end_2r2,
		size_2r2,
		tbit_2r2,
		fused_parent_2r2,
		id_preamble_2r2,
		inst_opcode_2r2,
		dsu_dispq_3free,
		
		////---------------------- Revised by sbc@2014-03-12 11:42 BEGIN----------------------
		ok_uop_vld_3r2,
		inst_end_3r2,
		size_3r2,
		tbit_3r2,
		fused_parent_3r2,
		id_preamble_3r2,
		inst_opcode_3r2,
		dsu_dispq_4free,
		////---------------------- Revised by sbc@2014-03-12 11:42 END------------------------
		dsu_vfu_uop_vld_jp2,
		dsu_vfu_gid_jp2,
		dsu_vfu_uop_ctl_jp2,
		ds_vfu_uop_sel_jp2,
		crypto_op_type_e1_q,
		crypto_aes_vld_e2_q,
		crypto_aes_issued_e1_q,
		crypto_rtag_e1_q,
		crypto_aes_gid_e1_q,
		crypto_aese_e1_q,
		crypto_aesd_e1_q,
		crypto_aese_out_e2_q,
		crypto_aesd_out_e2_q,
		
		uop_vld_0p2_q,
		uop_vld_1p2_q,
		uop_vld_2p2_q,
		
		uop_ctl_0p2_q,
		uop_ctl_1p2_q,
		uop_ctl_2p2_q,
		
		uop_itbits_0p2_q,
		uop_itbits_1p2_q,
		uop_itbits_2p2_q,
		
		itnoadv_0p2_q,
		itnoadv_1p2_q,
		itnoadv_2p2_q,
		
		ia_0p1,
		ia_1p1,
		ia_2p1,
		
		
		gid_0p2_q,
		gid_1p2_q,
		gid_2p2_q,
		
		inst_end_0p2_q,
		inst_end_1p2_q,
		inst_end_2p2_q,
		
		
		pre_end_0p2_q,
		pre_end_1p2_q,
		pre_end_2p2_q,
		
		ls0_uop_vld_0p2_q,
		ls0_uop_vld_1p2_q,
		ls0_uop_vld_2p2_q,
		ls1_uop_vld_0p2_q,
		ls1_uop_vld_1p2_q,
		ls1_uop_vld_2p2_q,
		
		mx0_uop_vld_0p2_q,
		mx0_uop_vld_1p2_q,
		mx0_uop_vld_2p2_q,
		mx1_uop_vld_0p2_q,
		mx1_uop_vld_1p2_q,
		mx1_uop_vld_2p2_q,
		
		cx0_uop_vld_0p2_q,
		cx0_uop_vld_1p2_q,
		cx0_uop_vld_2p2_q,
		cx1_uop_vld_0p2_q,
		cx1_uop_vld_1p2_q,
		cx1_uop_vld_2p2_q,
		
		sxj_uop_vld_0p2_q,
		sxj_uop_vld_1p2_q,
		sxj_uop_vld_2p2_q,
		sxk_uop_vld_0p2_q,
		sxk_uop_vld_1p2_q,
		sxk_uop_vld_2p2_q,
		
		bx_uop_vld_0p2_q,
		bx_uop_vld_1p2_q,
		bx_uop_vld_2p2_q,
		
		spr_uop_vld_0p2_q,
		spr_uop_vld_1p2_q,
		spr_uop_vld_2p2_q,
		
		dstx_tag_vld_0p2_q,
		dstx_tag_vld_1p2_q,
		dstx_tag_vld_2p2_q,
		

		`ifdef MAIA
		resq_wrenx_0p1,
		resq_wrenx_1p1,
		resq_wrenx_2p1,
		
		dstx_rtag_0p1_q,
		dstx_rtag_1p1_q,
		dstx_rtag_2p1_q,
		
		dstx_atag_0p1_q,
		dstx_atag_1p1_q,
		dstx_atag_2p1_q,
		
		dstx_dw_0p1_q,
		dstx_dw_1p1_q,
		dstx_dw_2p1_q,
		
		dstx_type_0p1_q,
		dstx_type_1p1_q,
		dstx_type_2p1_q,
		
		dstx_tag_vld_0p2_q,
		dstx_tag_vld_1p2_q,
		dstx_tag_vld_2p2_q,
		
		resq_wreny_0p1,
		resq_wreny_1p1,
		resq_wreny_2p1,
		
		dsty_rtag_0p1_q,
		dsty_rtag_1p1_q,
		dsty_rtag_2p1_q,
		
		dsty_atag_0p1_q,
		dsty_atag_1p1_q,
		dsty_atag_2p1_q,
		
		dsty_dw_0p1_q,
		dsty_dw_1p1_q,
		dsty_dw_2p1_q,
		
		dsty_type_0p1_q,
		dsty_type_1p1_q,
		dsty_type_2p1_q,
		`else

		resq_wrenx_0p2,
		resq_wrenx_1p2,
		resq_wrenx_2p2,
		
		dstx_rtag_0p2_q,
		dstx_rtag_1p2_q,
		dstx_rtag_2p2_q,
		
		dstx_atag_0p2_q,
		dstx_atag_1p2_q,
		dstx_atag_2p2_q,
		
		dstx_dw_0p2_q,
		dstx_dw_1p2_q,
		dstx_dw_2p2_q,
		
		dstx_type_0p2_q,
		dstx_type_1p2_q,
		dstx_type_2p2_q,
		
		resq_wreny_0p2,
		resq_wreny_1p2,
		resq_wreny_2p2,
		
		dsty_rtag_0p2_q,
		dsty_rtag_1p2_q,
		dsty_rtag_2p2_q,
		
		dsty_atag_0p2_q,
		dsty_atag_1p2_q,
		dsty_atag_2p2_q,
		
		dsty_dw_0p2_q,
		dsty_dw_1p2_q,
		dsty_dw_2p2_q,
		
		dsty_type_0p2_q,
		dsty_type_1p2_q,
		dsty_type_2p2_q,
		
		`endif

		dsty_tag_vld_0p2_q,
		dsty_tag_vld_1p2_q,
		dsty_tag_vld_2p2_q,
		
		resq_wrenp_0p2,
		resq_wrenp_1p2,
		resq_wrenp_2p2,
		////---------------------- Revised by sbc@2014-03-12 11:44 BEGIN----------------------
		uop_vld_3p2_q,
		uop_ctl_3p2_q,
		uop_itbits_3p2_q,
		itnoadv_3p2_q,
		ia_3p1,
		gid_3p2_q,
		inst_end_3p2_q,
		pre_end_3p2_q,
		ls0_uop_vld_3p2_q,
		ls1_uop_vld_3p2_q,
		mx0_uop_vld_3p2_q,
		mx1_uop_vld_3p2_q,
		cx0_uop_vld_3p2_q,
		cx1_uop_vld_3p2_q,
		sxj_uop_vld_3p2_q,
		sxk_uop_vld_3p2_q,
		bx_uop_vld_3p2_q,
		spr_uop_vld_3p2_q,
		resq_wrenx_3p2,
		dstx_rtag_3p2_q,
		dstx_atag_3p2_q,
		dstx_dw_3p2_q,
		dstx_type_3p2_q,
		dstx_tag_vld_3p2_q,
		resq_wreny_3p2,
		dsty_rtag_3p2_q,
		dsty_atag_3p2_q,
		dsty_dw_3p2_q,
		dsty_type_3p2_q,
		dsty_tag_vld_3p2_q,
		resq_wrenp_3p2,
		////---------------------- Revised by sbc@2014-03-12 11:44 END------------------------
		
		// arm register file
		arm_rf_data00b0_q,
		arm_rf_data01b0_q,
		arm_rf_data02b0_q,
		arm_rf_data03b0_q,
		arm_rf_data04b0_q,
		arm_rf_data05b0_q,
		arm_rf_data06b0_q,
		arm_rf_data07b0_q,
		arm_rf_data08b0_q,
		arm_rf_data09b0_q,
		arm_rf_data10b0_q,
		arm_rf_data11b0_q,
		arm_rf_data12b0_q,
		arm_rf_data13b0_q,
		arm_rf_data14b0_q,
		arm_rf_data15b0_q,
		arm_rf_data16b0_q,
		arm_rf_data17b0_q,
		arm_rf_data18b0_q,
		arm_rf_data19b0_q,
		arm_rf_data20b0_q,
		arm_rf_data21b0_q,
		arm_rf_data22b0_q,
		arm_rf_data23b0_q,
		arm_rf_data24b0_q,
		arm_rf_data25b0_q,
		arm_rf_data26b0_q,
		arm_rf_data27b0_q,
		arm_rf_data28b0_q,
		arm_rf_data29b0_q,
		arm_rf_data30b0_q,
		arm_rf_data31b0_q,
		arm_rf_data32b0_q,
		arm_rf_data33b0_q,
		arm_rf_data34b0_q,
		arm_rf_data35b0_q,
		arm_rf_data36b0_q,
		arm_rf_data37b0_q,
		arm_rf_data38b0_q,
		arm_rf_data39b0_q,
		arm_rf_data40b0_q,
		arm_rf_data41b0_q,
		
		arm_rf_data00b1_q,
		arm_rf_data01b1_q,
		arm_rf_data02b1_q,
		arm_rf_data03b1_q,
		arm_rf_data04b1_q,
		arm_rf_data05b1_q,
		arm_rf_data06b1_q,
		arm_rf_data07b1_q,
		arm_rf_data08b1_q,
		arm_rf_data09b1_q,
		arm_rf_data10b1_q,
		arm_rf_data11b1_q,
		arm_rf_data12b1_q,
		arm_rf_data13b1_q,
		arm_rf_data14b1_q,
		arm_rf_data15b1_q,
		arm_rf_data16b1_q,
		arm_rf_data17b1_q,
		arm_rf_data18b1_q,
		arm_rf_data19b1_q,
		arm_rf_data20b1_q,
		arm_rf_data21b1_q,
		arm_rf_data22b1_q,
		arm_rf_data23b1_q,
		arm_rf_data24b1_q,
		arm_rf_data25b1_q,
		arm_rf_data26b1_q,
		arm_rf_data27b1_q,
		arm_rf_data28b1_q,
		arm_rf_data29b1_q,
		arm_rf_data30b1_q,
		arm_rf_data31b1_q,
		arm_rf_data32b1_q,
		arm_rf_data33b1_q,
		arm_rf_data34b1_q,
		arm_rf_data35b1_q,
		arm_rf_data36b1_q,
		arm_rf_data37b1_q,
		arm_rf_data38b1_q,
		arm_rf_data39b1_q,
		arm_rf_data40b1_q,
		arm_rf_data41b1_q,
		
		// extension register file
		ext_rf_data00_b0_q,
		ext_rf_data00_b1_q,
		ext_rf_data01_b0_q,
		ext_rf_data01_b1_q,
		ext_rf_data02_b0_q,
		ext_rf_data02_b1_q,
		ext_rf_data03_b0_q,
		ext_rf_data03_b1_q,
		ext_rf_data04_b0_q,
		ext_rf_data04_b1_q,
		ext_rf_data05_b0_q,
		ext_rf_data05_b1_q,
		ext_rf_data06_b0_q,
		ext_rf_data06_b1_q,
		ext_rf_data07_b0_q,
		ext_rf_data07_b1_q,
		ext_rf_data08_b0_q,
		ext_rf_data08_b1_q,
		ext_rf_data09_b0_q,
		ext_rf_data09_b1_q,
		ext_rf_data10_b0_q,
		ext_rf_data10_b1_q,
		ext_rf_data11_b0_q,
		ext_rf_data11_b1_q,
		ext_rf_data12_b0_q,
		ext_rf_data12_b1_q,
		ext_rf_data13_b0_q,
		ext_rf_data13_b1_q,
		ext_rf_data14_b0_q,
		ext_rf_data14_b1_q,
		ext_rf_data15_b0_q,
		ext_rf_data15_b1_q,
		ext_rf_data16_b0_q,
		ext_rf_data16_b1_q,
		ext_rf_data17_b0_q,
		ext_rf_data17_b1_q,
		ext_rf_data18_b0_q,
		ext_rf_data18_b1_q,
		ext_rf_data19_b0_q,
		ext_rf_data19_b1_q,
		ext_rf_data20_b0_q,
		ext_rf_data20_b1_q,
		ext_rf_data21_b0_q,
		ext_rf_data21_b1_q,
		ext_rf_data22_b0_q,
		ext_rf_data22_b1_q,
		ext_rf_data23_b0_q,
		ext_rf_data23_b1_q,
		ext_rf_data24_b0_q,
		ext_rf_data24_b1_q,
		ext_rf_data25_b0_q,
		ext_rf_data25_b1_q,
		ext_rf_data26_b0_q,
		ext_rf_data26_b1_q,
		ext_rf_data27_b0_q,
		ext_rf_data27_b1_q,
		ext_rf_data28_b0_q,
		ext_rf_data28_b1_q,
		ext_rf_data29_b0_q,
		ext_rf_data29_b1_q,
		ext_rf_data30_b0_q,
		ext_rf_data30_b1_q,
		ext_rf_data31_b0_q,
		ext_rf_data31_b1_q,
		ext_rf_data32_b0_q,
		ext_rf_data32_b1_q,
		ext_rf_data33_b0_q,
		ext_rf_data33_b1_q,
		ext_rf_data00_b2_q,
		ext_rf_data00_b3_q,
		ext_rf_data01_b2_q,
		ext_rf_data01_b3_q,
		ext_rf_data02_b2_q,
		ext_rf_data02_b3_q,
		ext_rf_data03_b2_q,
		ext_rf_data03_b3_q,
		ext_rf_data04_b2_q,
		ext_rf_data04_b3_q,
		ext_rf_data05_b2_q,
		ext_rf_data05_b3_q,
		ext_rf_data06_b2_q,
		ext_rf_data06_b3_q,
		ext_rf_data07_b2_q,
		ext_rf_data07_b3_q,
		ext_rf_data08_b2_q,
		ext_rf_data08_b3_q,
		ext_rf_data09_b2_q,
		ext_rf_data09_b3_q,
		ext_rf_data10_b2_q,
		ext_rf_data10_b3_q,
		ext_rf_data11_b2_q,
		ext_rf_data11_b3_q,
		ext_rf_data12_b2_q,
		ext_rf_data12_b3_q,
		ext_rf_data13_b2_q,
		ext_rf_data13_b3_q,
		ext_rf_data14_b2_q,
		ext_rf_data14_b3_q,
		ext_rf_data15_b2_q,
		ext_rf_data15_b3_q,
		ext_rf_data16_b2_q,
		ext_rf_data16_b3_q,
		ext_rf_data17_b2_q,
		ext_rf_data17_b3_q,
		ext_rf_data18_b2_q,
		ext_rf_data18_b3_q,
		ext_rf_data19_b2_q,
		ext_rf_data19_b3_q,
		ext_rf_data20_b2_q,
		ext_rf_data20_b3_q,
		ext_rf_data21_b2_q,
		ext_rf_data21_b3_q,
		ext_rf_data22_b2_q,
		ext_rf_data22_b3_q,
		ext_rf_data23_b2_q,
		ext_rf_data23_b3_q,
		ext_rf_data24_b2_q,
		ext_rf_data24_b3_q,
		ext_rf_data25_b2_q,
		ext_rf_data25_b3_q,
		ext_rf_data26_b2_q,
		ext_rf_data26_b3_q,
		ext_rf_data27_b2_q,
		ext_rf_data27_b3_q,
		ext_rf_data28_b2_q,
		ext_rf_data28_b3_q,
		ext_rf_data29_b2_q,
		ext_rf_data29_b3_q,
		ext_rf_data30_b2_q,
		ext_rf_data30_b3_q,
		ext_rf_data31_b2_q,
		ext_rf_data31_b3_q,
		ext_rf_data32_b2_q,
		ext_rf_data32_b3_q,
		ext_rf_data33_b2_q,
		ext_rf_data33_b3_q,
		
		// psr register file
		psr_rf_data00_q,
		psr_rf_data01_q,
		psr_rf_data02_q,
		psr_rf_data03_q,
		
		// CP14 registers
		teecr,
		teehbr,
		jidr,
		joscr,
		jmcr,
		
		// CP15 registers
		isr,
		midr,
		ctr,
		tcmtr,
		tlbtr,
		mpidr,
		dec_pfr0,
		dec_pfr1,
		dec_dfr0,
		dec_afr0,
		dec_mmfr0,
		dec_mmfr1,
		dec_mmfr2,
		dec_mmfr3,
		dec_isar0,
		dec_isar1,
		dec_isar2,
		dec_isar3,
		dec_isar4,
		dec_isar5,
		ccsidr,
		clidr,
		aidr,
		csselr_ns,
		csselr_s,
		vpidr,
		vmpidr,
		sctlr_ns,
		sctlr_s,
		actlr_s,
		actlr_ns,
		cpuactlr_el1,
		cptr_el3,
		mdcr_el3,
		cpacr,
		scr,
		sder,
		nsacr,
		hsctlr,
		hactlr,
		hcr,
		hcr2,
		hdcr,
		hcptr,
		hstr,
		hacr,
		ttbr0_hi_s,
		ttbr0_hi_ns,
		ttbr0_lo_s,
		ttbr0_lo_ns,
		ttbr1_hi_s,
		ttbr1_hi_ns,
		ttbr1_lo_s,
		ttbr1_lo_ns,
		ttbcr_s,
		ttbcr_ns,
		tcr_el1,
		tcr_el2,
		tcr_el3,
		vtcr_el2,
		vbar_el1,
		isr_el1,
		vbar_el2,
		vbar_el3,
		rvbar_el3,
		rmr_el3,
		tpidr_el0,
		tpidr_el1,
		tpidr_el2,
		tpidr_el3,
		tpidrro_el0,
		htcr,
		vtcr,
		dacr_s,
		dacr_ns,
		dfsr_s,
		dfsr_ns,
		ifsr_s,
		ifsr_ns,
		adfsr_s,
		adfsr_ns,
		aifsr_s,
		aifsr_ns,
		hadfsr,
		haifsr,
		hsr,
		dfar_s,
		dfar_ns,
		ifar_s,
		ifar_ns,
		hdfar,
		hifar,
		hpfar,
		hpfar_el2,
		far_el3,
		prrr_mair0_s,
		prrr_mair0_ns,
		nmrr_mair1_s,
		nmrr_mair1_ns,
		amair0_s,
		amair0_ns,
		amair1_s,
		amair1_ns,
		hmair0,
		hmair1,
		hamair0,
		hamair1,
		vbar_s,
		vbar_ns,
		mvbar,
		hvbar,
		fcseidr,
		contextidr_s,
		contextidr_ns,
		tpidrurw_s,
		tpidrurw_ns,
		tpidruro_s,
		tpidruro_ns,
		tpidrprw_s,
		tpidrprw_ns,
		htpidr,
		vttbr_hi,
		vttbr_lo,
		httbr_hi,
		httbr_lo,
		
		if_spr_wr_data_e2_q,
		ls_spr_wr_data_e2_q,
		l2_spr_wr_data_e2_q,
		dt_spr_wr_data_e2_q,
		
		sb_mux_merge_store_s2,
		sb_mux_dcz_s2,
		sb_mux_gid_s2,
		sb_mux_attr_s2,
		st_mux_bv_s2,
		sb_mux_data_s2,
		sb_mux_pa_s2,
		sb_mux_first_s2,
		sb_mux_second_s2,
		sb_mux_split_cnt_s2,
		store_done_int_s2,
		
		cpsr32,
		cpsr64,
		dsu_aarch64_state,
		dsu_flush_trgt_aarch64,
		fpexc,
		fpscr,
		dspsr,
		mvfr0,
		mvfr1,
		mvfr2,
		dec_aa64pfr0_el1,
		dec_aa64pfr1_el1,
		dec_aa64dfr0_el1,
		dec_aa64dfr1_el1,
		dec_aa64afr0_el1,
		dec_aa64afr1_el1,
		dec_aa64isar0_el1,
		dec_aa64isar1_el1,
		dec_aa64mmfr0_el1,
		dec_aa64mmfr1_el1,
		fpsid,
		spsr_el1,
		spsr_el2,
		spsr_el3,
		spsr_svc,
		spsr_mon,
		spsr_abt,
		spsr_und,
		spsr_irq,
		spsr_fiq,
		spsr_hyp,
		
		sp_uop_vld_i1,
		sp_uop_ctl_i1,
		sp_uop_wdata_i1,
		sp_uop_ns_i1,
		sp_resolved_ccpass_i1,
		sp_sync_done_i1,
		
		sp_uop_vld_p3,
		sp_uop_gid_p3,
		sp_wfi_p3_q,
		sp_wfe_p3_q,
		wfi_wakeup_active,
		wfe_wakeup_active,
		
		

		`ifdef CORE_TESTBENCH//{
		lsu_resx_tag_vld_w1,
		lsu_resx_tag_w1,
		lsu_resy_tag_vld_w1,
		lsu_resy_tag_w1,
		tb_lsu_ld_j,
		tb_lsu_ld_va_j,
		tb_lsu_ld_tag_j,
		tb_lsu_ld_k,
		tb_lsu_ld_va_k,
		tb_lsu_ld_tag_k,
		`else //  CORE_TESTBENCH

		lsu_resx_tag_vld_w0,
		dstx_tag_ld_e2,
		lsu_resy_tag_vld_w0,
		dsty_tag_ld_e2,
		`endif//} //  CORE_TESTBENCH

		lsu_resx_dw_w1,
		lsu_resx_data_w2,
		lsu_resx_data_cancel_w1,
		lsu_resy_dw_w1,
		lsu_resy_data_w2,
		lsu_resy_data_cancel_w1,
		lsu_resolved_j,
		lsu_pa_ld_e4,
		lsu_va_ld_e2,
		lsu_page_attr_ld_e4,
		lsu_cache_attr_ld_e4,
		lsu_shared_attr_ld_e4,
		spo_read_par_s2,
		sext_ld_e4,
		big_endian_ld_e4,
		element_size_ld_e4,
		iq_ld_alloc_fb_e4,
		sodev_ex_ld_e4,
		ls_ccpass_ld_e5,
		unal_second_ld_e3,
		strex_force_ld_e4,
		rst_strex_req_e2,
		rst_strex_pass_e2,
		sb_mux_strex_s2,
		sb_new_strex_lastm_s3,
		sb_mux_atomic_firstm_s2,
		sb_mux_atomic_2nd_s2,
		
		lsu_va_st_e2,
		valid_st_e2,
		ls_sb_shift,
		sb_gid_st_e2,
		second_half_st_restart_e2,
		uop_type_st_e2,
		
		l2_cpu_dext_err_r2,
		l2_cpu_dvalid_r1,
		l2_cpu_dbufid_r1,
		fb0_pa,
		fb1_pa,
		fb2_pa,
		fb3_pa,
		fb4_pa,
		fb5_pa,
		
		bru_resolved,
		bru_resolved_gid,
		bru_mispred_addr_e2,
		
		dsu_commit_0c1,
		dsu_commit_1c1,
		dsu_commit_gid_0c1,
		dsu_commit_gid_1c1,
		dealloc_update_0_q,
		dealloc_update_1_q,
		
		commq_dealloc_t_update_0,
		commq_dealloc_t_update_1,
		commq_dealloc_it_update_0,
		commq_dealloc_it_update_1,
		commq_dealloc_q_update_0,
		commq_dealloc_q_update_1,
		commq_dealloc_qf_update_0,
		commq_dealloc_qf_update_1,
		commq_dealloc_ss_clr_0,
		commq_dealloc_ss_clr_1,
		commq_dealloc_gid_q,
		
		bru_flush,
		bru_flush_gid,
		dsu_flush,
		debug_start,
		debug_state,
		mbist_state,
		dsu_prestart,
		dsu_ia_restart,
		dsu_flush_type,
		prc_pabort_stg2_x1_q,
		prc_dabort_stg2_x1_q,
		prc_dabort_algn_x1_q,
		prc_dabort_sp_x1_q,
		dsu_flush_gid,

		`ifdef PRJ_SKYROS_INTERFACE//{
		l2_feq_comp_set_compdbidresp,
		l2_feq_comp_set_compresp,
		l2_feq_axi_wr_state_q,
		l2_rxrsp_resperr_q,
		l2_feq0_addr_q,
		l2_feq1_addr_q,
		l2_feq2_addr_q,
		l2_feq3_addr_q,
		l2_feq4_addr_q,
		l2_feq5_addr_q,
		l2_feq6_addr_q,
		l2_feq7_addr_q,
		l2_feq8_addr_q,
		l2_feq9_addr_q,
		l2_feq10_addr_q,
		l2_feq11_addr_q,
		l2_feq12_addr_q,
		l2_feq13_addr_q,
		l2_feq14_addr_q,

		`ifndef MAIA

		`ifdef FEQ20
		l2_feq15_addr_q,
		l2_feq16_addr_q,
		l2_feq17_addr_q,
		l2_feq18_addr_q,
		l2_feq19_addr_q
		`else

		l2_feq15_addr_q
		`endif

		`else

		l2_feq15_addr_q,
		l2_feq16_addr_q,
		l2_feq17_addr_q,
		l2_feq18_addr_q,
		l2_feq19_addr_q,
		l2_feq20_addr_q,
		l2_feq21_addr_q,
		l2_feq22_addr_q,
		l2_feq23_addr_q
		`endif

		
		`else

		l2_bvalid_q,
		l2_bresp_q,
		l2_bid_q,
		l2_asq_bid_match,
		l2_asq0_addr_q,
		l2_asq1_addr_q,
		l2_asq2_addr_q,
		l2_asq3_addr_q,
		l2_asq4_addr_q,
		l2_asq5_addr_q,
		l2_asq6_addr_q,
		l2_asq7_addr_q,
		l2_asq8_addr_q,
		l2_asq9_addr_q,
		l2_asq10_addr_q,
		l2_asq11_addr_q,
		l2_asq12_addr_q,
		l2_asq13_addr_q,
		l2_asq14_addr_q,
		l2_asq15_addr_q
		`endif//}

		);
	
	input [1:0]	cpuid;
	input [7:0]	clusterid_init;
	input		ck_gclkcr;
	input [31:0]    cycle;
	input		reset;
	input		cp15sdisable;
	
	input           cfgte;
	input           vinithi;
	input           cfgend;
	input           iminln;
	input [43:15]	periphbase;
	
	output		iss_mismatch;
	output		iss_fatal;
	output		iss_eot;
	
	input [7:0]	ds_aes_restore_atag_0t1;
	input [7:0]	ds_aes_restore_atag_1t1;
	input [7:0]	ds_aes_restore_atag_2t1;
	input [7:0]	ds_aes_restore_atag_3t1;
	input [7:0]	ds_aes_restore_atag_4t1;
	input [7:0]	ds_aes_restore_atag_5t1;
	input		ds_aes_restore_dw_0t1;
	input		ds_aes_restore_dw_1t1;
	input		ds_aes_restore_dw_2t1;
	input		ds_aes_restore_dw_3t1;
	input		ds_aes_restore_dw_4t1;
	input		ds_aes_restore_dw_5t1;
	input [`XM_AES_RTAG_INDEX-1:0]	ds_aes_restore_rtag_0t0_0u2;
	input [`XM_AES_RTAG_INDEX-1:0]	ds_aes_restore_rtag_1t0_1u2;
	input [`XM_AES_RTAG_INDEX-1:0]	ds_aes_restore_rtag_2t0_2u2;
	input [`XM_AES_RTAG_INDEX-1:0]	ds_aes_restore_rtag_3t0_3u2;
	input [`XM_AES_RTAG_INDEX-1:0]	ds_aes_restore_rtag_4t0_4u2;
	input [`XM_AES_RTAG_INDEX-1:0]	ds_aes_restore_rtag_5t0_5u2;
	input [2:0]	ds_aes_restore_type_0t1;
	input [2:0]	ds_aes_restore_type_1t1;
	input [2:0]	ds_aes_restore_type_2t1;
	input [2:0]	ds_aes_restore_type_3t1;
	input [2:0]	ds_aes_restore_type_4t1;
	input [2:0]	ds_aes_restore_type_5t1;
	input [3:0]	ds_aes_restore_zbits_0t1;
	input [3:0]	ds_aes_restore_zbits_1t1;
	input [3:0]	ds_aes_restore_zbits_2t1;
	input [3:0]	ds_aes_restore_zbits_3t1;
	input [3:0]	ds_aes_restore_zbits_4t1;
	input [3:0]	ds_aes_restore_zbits_5t1;
	input		ds_aes_retire_vld_0t0;
	input		ds_aes_retire_vld_1t0;
	input		ds_aes_retire_vld_2t0;
	input		ds_aes_retire_vld_3t0;
	input		ds_aes_retire_vld_4t0;
	input		ds_aes_retire_vld_5t0;
	
	input [31:0]    arm_resq_ret_data_0t2_q;
	input [31:0]    arm_resq_ret_data_1t2_q;
	input [31:0]    arm_resq_ret_data_2t2_q;
	input [31:0]    arm_resq_ret_data_3t2_q;
	input [31:0]    arm_resq_ret_data_4t2_q;

	`ifdef MAIA
	input [31:0]    arm_resq_ret_data_5t2_q;
	`endif

	input [31:0]    ext_resq_ret_data_0t2_q;
	input [31:0]    ext_resq_ret_data_1t2_q;
	input [31:0]    ext_resq_ret_data_2t2_q;
	input [31:0]    ext_resq_ret_data_3t2_q;
	input [31:0]    ext_resq_ret_data_4t2_q;

	`ifdef MAIA
	input [31:0]    ext_resq_ret_data_5t2_q;
	`endif

	
	input [2:0]	ds_psr_restore_atag_0t0_0u2;
	input [2:0]	ds_psr_restore_atag_1t0_1u2;
	input [2:0]	ds_psr_restore_atag_2t0_2u2;
	input [4:0]	ds_psr_restore_rtag_0t0_0u2;
	input [4:0]	ds_psr_restore_rtag_1t0_1u2;
	input [4:0]	ds_psr_restore_rtag_2t0_2u2;
	input		ds_psr_retire_vld_0t0;
	input		ds_psr_retire_vld_1t0;
	input		ds_psr_retire_vld_2t0;
	input [3:0]   ds_psr_ret_data_0t2_q;
	input [3:0]   ds_psr_ret_data_1t2_q;
	
	
	//D1:Capture Opcode
	input   ifu_size_0d1;
	input   ifu_size_1d1;
	input   ifu_size_2d1;
	
	input   ifu_tbit_0d1;
	input   ifu_tbit_1d1;
	input   ifu_tbit_2d1;
	
	input   ifu_vld_0d1;
	input   ifu_vld_1d1;
	input   ifu_vld_2d1;
	
	input   dec_genq_1free;
	input   dec_genq_2free;
	input   dec_genq_3free;
	
	input [31:16] ifu_inst_h_0d1;
	input [31:16] ifu_inst_h_1d1;
	input [31:16] ifu_inst_h_2d1;
	
	input [15:0] ifu_inst_l_0d1;
	input [15:0] ifu_inst_l_1d1;
	input [15:0] ifu_inst_l_2d1;
	
	input   ifu_pcalgn_abt_pend;
	
	//R2:Capture Fusion
	input        ok_uop_vld_0r2;
	input        inst_end_0r2;
	input        size_0r2;
	input        tbit_0r2;
	input        fused_parent_0r2;
	input        id_preamble_0r2;
	input [31:0] inst_opcode_0r2;
	input        dsu_dispq_1free;
	
	input        ok_uop_vld_1r2;
	input        inst_end_1r2;
	input        size_1r2;
	input        tbit_1r2;
	input        fused_parent_1r2;
	input        id_preamble_1r2;
	input [31:0] inst_opcode_1r2;
	input        dsu_dispq_2free;
	
	input        ok_uop_vld_2r2;
	input        inst_end_2r2;
	input        size_2r2;
	input        tbit_2r2;
	input        fused_parent_2r2;
	input        id_preamble_2r2;
	input [31:0] inst_opcode_2r2;
	input        dsu_dispq_3free;
	
	////---------------------- Revised by sbc@2014-03-12 11:51 BEGIN----------------------
	input        ok_uop_vld_3r2;
	input        inst_end_3r2;
	input        size_3r2;
	input        tbit_3r2;
	input        fused_parent_3r2;
	input        id_preamble_3r2;
	input [31:0] inst_opcode_3r2;
	input        dsu_dispq_4free;
	////---------------------- Revised by sbc@2014-03-12 11:51 END------------------------
	
	input          dsu_vfu_uop_vld_jp2;
	input [6:0]    dsu_vfu_gid_jp2;
	input [63:0]   dsu_vfu_uop_ctl_jp2;
	input [2:0]    ds_vfu_uop_sel_jp2;
	input [4:0]    crypto_op_type_e1_q;
	input          crypto_aes_vld_e2_q;
	input          crypto_aes_issued_e1_q;
	input [`XM_AES_RTAG_INDEX-1:0]    crypto_rtag_e1_q;
	input [6:0]    crypto_aes_gid_e1_q;
	input          crypto_aese_e1_q;
	input          crypto_aesd_e1_q;
	input [127:0]  crypto_aese_out_e2_q;
	input [127:0]  crypto_aesd_out_e2_q;
	
	input		uop_vld_0p2_q;
	input		uop_vld_1p2_q;
	input		uop_vld_2p2_q;
	
	input [63:0]	uop_ctl_0p2_q;
	input [63:0]	uop_ctl_1p2_q;
	input [63:0]	uop_ctl_2p2_q;
	
	input [7:0]	uop_itbits_0p2_q;
	input [7:0]	uop_itbits_1p2_q;
	input [7:0]	uop_itbits_2p2_q;
	
	input itnoadv_0p2_q;
	input itnoadv_1p2_q;
	input itnoadv_2p2_q;
	
	input [63:0]	ia_0p1;
	input [63:0]	ia_1p1;
	input [63:0]	ia_2p1;
	
	
	input [6:0]	gid_0p2_q;
	input [6:0]	gid_1p2_q;
	input [6:0]	gid_2p2_q;
	
	input		inst_end_0p2_q;
	input		inst_end_1p2_q;
	input		inst_end_2p2_q;
	
	
	input   	pre_end_0p2_q;
	input		pre_end_1p2_q;
	input		pre_end_2p2_q;
	
	input		ls0_uop_vld_0p2_q;
	input		ls0_uop_vld_1p2_q;
	input		ls0_uop_vld_2p2_q;
	input		ls1_uop_vld_0p2_q;
	input		ls1_uop_vld_1p2_q;
	input		ls1_uop_vld_2p2_q;
	
	input		mx0_uop_vld_0p2_q;
	input		mx0_uop_vld_1p2_q;
	input		mx0_uop_vld_2p2_q;
	input		mx1_uop_vld_0p2_q;
	input		mx1_uop_vld_1p2_q;
	input		mx1_uop_vld_2p2_q;
	
	input		cx0_uop_vld_0p2_q;
	input		cx0_uop_vld_1p2_q;
	input		cx0_uop_vld_2p2_q;
	input		cx1_uop_vld_0p2_q;
	input		cx1_uop_vld_1p2_q;
	input		cx1_uop_vld_2p2_q;
	
	input		sxj_uop_vld_0p2_q;
	input		sxj_uop_vld_1p2_q;
	input		sxj_uop_vld_2p2_q;
	input		sxk_uop_vld_0p2_q;
	input		sxk_uop_vld_1p2_q;
	input		sxk_uop_vld_2p2_q;
	
	input		bx_uop_vld_0p2_q;
	input		bx_uop_vld_1p2_q;
	input		bx_uop_vld_2p2_q;
	
	input		spr_uop_vld_0p2_q;
	input		spr_uop_vld_1p2_q;
	input		spr_uop_vld_2p2_q;
	
	input		dstx_tag_vld_0p2_q;
	input		dstx_tag_vld_1p2_q;
	input		dstx_tag_vld_2p2_q;
	
	

	`ifdef MAIA
	input		resq_wrenx_0p1;
	input		resq_wrenx_1p1;
	input		resq_wrenx_2p1;
	
	input [`XM_AES_RTAG_INDEX-1:0]	dstx_rtag_0p1_q;
	input [`XM_AES_RTAG_INDEX-1:0]	dstx_rtag_1p1_q;
	input [`XM_AES_RTAG_INDEX-1:0]	dstx_rtag_2p1_q;
	
	input [7:0]	dstx_atag_0p1_q;
	input [7:0]	dstx_atag_1p1_q;
	input [7:0]	dstx_atag_2p1_q;
	
	input		dstx_dw_0p1_q;
	input		dstx_dw_1p1_q;
	input		dstx_dw_2p1_q;
	
	input [2:0]	dstx_type_0p1_q;
	input [2:0]	dstx_type_1p1_q;
	input [2:0]	dstx_type_2p1_q;
	
	
	input		resq_wreny_0p1;
	input		resq_wreny_1p1;
	input		resq_wreny_2p1;
	
	input [`XM_AES_RTAG_INDEX-1:0]	dsty_rtag_0p1_q;
	input [`XM_AES_RTAG_INDEX-1:0]	dsty_rtag_1p1_q;
	input [`XM_AES_RTAG_INDEX-1:0]	dsty_rtag_2p1_q;
	
	input [7:0]	dsty_atag_0p1_q;
	input [7:0]	dsty_atag_1p1_q;
	input [7:0]	dsty_atag_2p1_q;
	
	input		dsty_dw_0p1_q;
	input		dsty_dw_1p1_q;
	input		dsty_dw_2p1_q;
	
	input [2:0]	dsty_type_0p1_q;
	input [2:0]	dsty_type_1p1_q;
	input [2:0]	dsty_type_2p1_q;
	`else

	input		resq_wrenx_0p2;
	input		resq_wrenx_1p2;
	input		resq_wrenx_2p2;
	
	input [`XM_AES_RTAG_INDEX-1:0]	dstx_rtag_0p2_q;
	input [`XM_AES_RTAG_INDEX-1:0]	dstx_rtag_1p2_q;
	input [`XM_AES_RTAG_INDEX-1:0]	dstx_rtag_2p2_q;
	
	input [7:0]	dstx_atag_0p2_q;
	input [7:0]	dstx_atag_1p2_q;
	input [7:0]	dstx_atag_2p2_q;
	
	input		dstx_dw_0p2_q;
	input		dstx_dw_1p2_q;
	input		dstx_dw_2p2_q;
	
	input [2:0]	dstx_type_0p2_q;
	input [2:0]	dstx_type_1p2_q;
	input [2:0]	dstx_type_2p2_q;
	
	input		resq_wreny_0p2;
	input		resq_wreny_1p2;
	input		resq_wreny_2p2;
	
	input [`XM_AES_RTAG_INDEX-1:0]	dsty_rtag_0p2_q;
	input [`XM_AES_RTAG_INDEX-1:0]	dsty_rtag_1p2_q;
	input [`XM_AES_RTAG_INDEX-1:0]	dsty_rtag_2p2_q;
	
	input [7:0]	dsty_atag_0p2_q;
	input [7:0]	dsty_atag_1p2_q;
	input [7:0]	dsty_atag_2p2_q;
	
	input		dsty_dw_0p2_q;
	input		dsty_dw_1p2_q;
	input		dsty_dw_2p2_q;
	
	input [2:0]	dsty_type_0p2_q;
	input [2:0]	dsty_type_1p2_q;
	input [2:0]	dsty_type_2p2_q;
	`endif

	
	input		dsty_tag_vld_0p2_q;
	input		dsty_tag_vld_1p2_q;
	input		dsty_tag_vld_2p2_q;
	
	input		resq_wrenp_0p2;
	input		resq_wrenp_1p2;
	input		resq_wrenp_2p2;
	
	////---------------------- Revised by sbc@2014-03-12 11:52 BEGIN----------------------
	input		uop_vld_3p2_q;
	input [63:0]	uop_ctl_3p2_q;
	input [7:0]	uop_itbits_3p2_q;
	input itnoadv_3p2_q;
	input [63:0]	ia_3p1;
	input [6:0]	gid_3p2_q;
	input		inst_end_3p2_q;
	input		pre_end_3p2_q;
	input		ls0_uop_vld_3p2_q;
	input		ls1_uop_vld_3p2_q;
	input		mx0_uop_vld_3p2_q;
	input		mx1_uop_vld_3p2_q;
	input		cx0_uop_vld_3p2_q;
	input		cx1_uop_vld_3p2_q;
	input		sxj_uop_vld_3p2_q;
	input		sxk_uop_vld_3p2_q;
	input		bx_uop_vld_3p2_q;
	input		spr_uop_vld_3p2_q;
	input		resq_wrenx_3p2;
	input [`XM_AES_RTAG_INDEX-1:0]	dstx_rtag_3p2_q;
	input [7:0]	dstx_atag_3p2_q;
	input		dstx_dw_3p2_q;
	input [2:0]	dstx_type_3p2_q;
	input		dstx_tag_vld_3p2_q;
	input		resq_wreny_3p2;
	input [`XM_AES_RTAG_INDEX-1:0]	dsty_rtag_3p2_q;
	input [7:0]	dsty_atag_3p2_q;
	input		dsty_dw_3p2_q;
	input [2:0]	dsty_type_3p2_q;
	input		dsty_tag_vld_3p2_q;
	input		resq_wrenp_3p2;
	////---------------------- Revised by sbc@2014-03-12 11:52 END------------------------
	
	// CP15 registers
	input   [31:0]  midr;
	input   [31:0]  ctr;
	input   [31:0]  tcmtr;
	input   [31:0]  tlbtr;
	input   [31:0]  mpidr;
	input   [31:0]  dec_pfr0;
	input   [31:0]  dec_pfr1;
	input   [31:0]  dec_dfr0;
	input   [31:0]  dec_afr0;
	input   [31:0]  dec_mmfr0;
	input   [31:0]  dec_mmfr1;
	input   [31:0]  dec_mmfr2;
	input   [31:0]  dec_mmfr3;
	input   [31:0]  dec_isar0;
	input   [31:0]  dec_isar1;
	input   [31:0]  dec_isar2;
	input   [31:0]  dec_isar3;
	input   [31:0]  dec_isar4;
	input   [31:0]  dec_isar5;
	input   [31:0]  ccsidr;
	input   [31:0]  clidr;
	input   [31:0]  aidr;
	
	input	[31:0]	csselr_ns;
	input	[31:0]	csselr_s;
	input	[31:0]	vpidr;
	input	[31:0]	vmpidr;
	input	[31:0]	sctlr_ns;
	input	[31:0]	sctlr_s;
	input	[31:0]	actlr_s;
	input	[31:0]	actlr_ns;
	input	[31:0]	cpuactlr_el1;
	input	[31:0]	cptr_el3;
	input	[31:0]	mdcr_el3;
	input	[31:0]	cpacr;
	input	[31:0]	scr;
	input	[31:0]	sder;
	input	[31:0]	nsacr;
	input	[31:0]	hsctlr;
	input	[31:0]	hactlr;
	input	[31:0]	hcr;
	input	[31:0]	hcr2;
	input	[31:0]	hdcr;
	input	[31:0]	hcptr;
	input	[31:0]	hstr;
	input	[31:0]	hacr;
	input	[31:0]	ttbr0_lo_ns;
	input	[31:0]	ttbr0_lo_s;
	input	[31:0]	ttbr0_hi_ns;
	input	[31:0]	ttbr0_hi_s;
	input	[31:0]	ttbr1_lo_ns;
	input	[31:0]	ttbr1_lo_s;
	input	[31:0]	ttbr1_hi_ns;
	input	[31:0]	ttbr1_hi_s;
	input	[31:0]	ttbcr_ns;
	input	[31:0]	ttbcr_s;
	input	[63:0]	tcr_el1;
	input	[63:0]	tcr_el2;
	input	[63:0]	vtcr_el2;
	input	[63:0]	tcr_el3;
	input	[63:0]	vbar_el1;
	input	[63:0]	isr_el1;
	input	[63:0]	vbar_el2;
	input	[63:0]	vbar_el3;
	input	[63:0]  rvbar_el3;
	input	[63:0]  rmr_el3;
	input	[63:0]  tpidr_el0;
	input	[63:0]  tpidr_el1;
	input	[63:0]  tpidr_el2;
	input	[63:0]  tpidr_el3;
	input	[63:0]  tpidrro_el0;
	input	[31:0]	htcr;
	input	[31:0]	vtcr;
	input	[31:0]	dacr_ns;
	input	[31:0]	dacr_s;
	input	[31:0]	dfsr_ns;
	input	[31:0]	dfsr_s;
	input	[31:0]	ifsr_ns;
	input	[31:0]	ifsr_s;
	input	[31:0]	adfsr_ns;
	input	[31:0]	adfsr_s;
	input	[31:0]	aifsr_ns;
	input	[31:0]	aifsr_s;
	input	[31:0]	hadfsr;
	input	[31:0]	haifsr;
	input	[31:0]	hsr;
	input	[31:0]	dfar_ns;
	input	[31:0]	dfar_s;
	input	[31:0]	ifar_ns;
	input	[31:0]	ifar_s;
	input	[31:0]	hdfar;
	input	[31:0]	hifar;
	input	[31:0]	hpfar;
	input	[63:0]	hpfar_el2;
	input	[63:0]	far_el3;
	input	[31:0]	prrr_mair0_ns;
	input	[31:0]	prrr_mair0_s;
	input	[31:0]	nmrr_mair1_ns;
	input	[31:0]	nmrr_mair1_s;
	input	[31:0]	amair0_s;
	input	[31:0]	amair0_ns;
	input	[31:0]	amair1_s;
	input	[31:0]	amair1_ns;
	input	[31:0]	hmair0;
	input	[31:0]	hmair1;
	input	[31:0]	hamair0;
	input	[31:0]	hamair1;
	input	[31:0]	vbar_ns;
	input	[31:0]	vbar_s;
	input	[31:0]	mvbar;
	input   [31:0]  isr;
	input	[31:0]	hvbar;
	input	[31:0]	fcseidr;
	input	[31:0]	contextidr_ns;
	input	[31:0]	contextidr_s;
	input	[31:0]	tpidrurw_ns;
	input	[31:0]	tpidrurw_s;
	input	[31:0]	tpidruro_ns;
	input	[31:0]	tpidruro_s;
	input	[31:0]	tpidrprw_ns;
	input	[31:0]	tpidrprw_s;
	input	[31:0]	htpidr;
	
	// local cp15rr
	input	[31:0]	vttbr_lo;
	input	[31:0]	vttbr_hi;
	input	[31:0]	httbr_lo;
	input	[31:0]	httbr_hi;
	
	// local CP14 registers
	input [31:0]  teecr;
	input [31:0]  jidr;
	input [31:0]  teehbr;
	input [31:0]  joscr;
	input [31:0]  jmcr;
	
	input	[63:0]	if_spr_wr_data_e2_q;
	input	[63:0]	l2_spr_wr_data_e2_q;
	input	[63:0]	ls_spr_wr_data_e2_q;
	input	[63:0]	dt_spr_wr_data_e2_q;
	
	
	input			sb_mux_merge_store_s2;
	input                   sb_mux_dcz_s2;
	input  [6:0]            sb_mux_gid_s2;
	input [12:0]		sb_mux_attr_s2;
	input [15:0]		st_mux_bv_s2;
	input [63:0]		sb_mux_data_s2;
	input [44:0]		sb_mux_pa_s2;
	input			sb_mux_first_s2;
	input			sb_mux_second_s2;
	input [1:0]             sb_mux_split_cnt_s2;
	input			store_done_int_s2;
	
	

	`ifdef CORE_TESTBENCH//{
	input		lsu_resx_tag_vld_w1;
	input [`XM_AES_RTAG_INDEX-1:0]	lsu_resx_tag_w1;
	input		lsu_resy_tag_vld_w1;
	input [`XM_AES_RTAG_INDEX-1:0]	lsu_resy_tag_w1;
	`else

	input		lsu_resx_tag_vld_w0;
	input [`XM_AES_RTAG_INDEX-1:0]	dstx_tag_ld_e2;
	input		lsu_resy_tag_vld_w0;
	input [`XM_AES_RTAG_INDEX-1:0]	dsty_tag_ld_e2;
	`endif//}

	input		lsu_resx_dw_w1;
	input [63:0]	lsu_resx_data_w2;
	input		lsu_resx_data_cancel_w1;
	input		lsu_resy_dw_w1;
	input [63:0]	lsu_resy_data_w2;
	input		lsu_resy_data_cancel_w1;
	input		lsu_resolved_j;
	input [44:0]	lsu_pa_ld_e4;
	input [63:0]	lsu_va_ld_e2;
	input [7:0]	lsu_page_attr_ld_e4;
	input [2:0]	lsu_cache_attr_ld_e4;
	input [1:0]	lsu_shared_attr_ld_e4;
	input           spo_read_par_s2;
	input		sext_ld_e4;
	input           big_endian_ld_e4;
	input [2:0]     element_size_ld_e4;
	input [1:0]	iq_ld_alloc_fb_e4;
	input		sodev_ex_ld_e4;
	input		ls_ccpass_ld_e5;
	input		unal_second_ld_e3;
	input		strex_force_ld_e4;
	input		rst_strex_req_e2;
	input		rst_strex_pass_e2;
	input		sb_mux_strex_s2;
	input           sb_new_strex_lastm_s3;
	input           sb_mux_atomic_firstm_s2;
	input		sb_mux_atomic_2nd_s2;
	
	input	[63:0]	lsu_va_st_e2;
	input		valid_st_e2;
	input	[11:0]	ls_sb_shift;
	input	[6:0]	sb_gid_st_e2;
	input           second_half_st_restart_e2;
	input	[3:0]	uop_type_st_e2;
	
	input		bru_resolved;
	input	 [5:0]	bru_resolved_gid;
	input	[31:0]	bru_mispred_addr_e2;
	
	input		dsu_commit_0c1;
	input		dsu_commit_1c1;
	input [6:0]	dsu_commit_gid_0c1;
	input [6:0]	dsu_commit_gid_1c1;
	input		dealloc_update_0_q;
	input		dealloc_update_1_q;
	
	input         commq_dealloc_t_update_0;
	input         commq_dealloc_t_update_1;
	input         commq_dealloc_it_update_0;
	input         commq_dealloc_it_update_1;
	input         commq_dealloc_q_update_0;
	input         commq_dealloc_q_update_1;
	input         commq_dealloc_qf_update_0;
	input         commq_dealloc_qf_update_1;
	input         commq_dealloc_ss_clr_0;
	input         commq_dealloc_ss_clr_1;
	input [6:0] commq_dealloc_gid_q;
	
	input		bru_flush;
	input [6:0]	bru_flush_gid;
	input		debug_start;
	input		debug_state;
	input   mbist_state;
	input		dsu_flush;
	input		dsu_prestart;
	input           dsu_ia_restart;
	input [6:0]	dsu_flush_gid;
	input [5:0]	dsu_flush_type;
	input       prc_pabort_stg2_x1_q;
	input       prc_dabort_stg2_x1_q;
	input       prc_dabort_algn_x1_q;
	input       prc_dabort_sp_x1_q;
	

	`ifdef PRJ_SKYROS_INTERFACE//{
	//L2 FEQ
	input [`FEQ_MSB:0] l2_feq_comp_set_compdbidresp;
	input [`FEQ_MSB:0] l2_feq_comp_set_compresp;
	input [`FEQ_MSB:0] l2_feq_axi_wr_state_q;
	input [1:0]  l2_rxrsp_resperr_q;
	input [44:0] l2_feq0_addr_q;
	input [44:0] l2_feq1_addr_q;
	input [44:0] l2_feq2_addr_q;
	input [44:0] l2_feq3_addr_q;
	input [44:0] l2_feq4_addr_q;
	input [44:0] l2_feq5_addr_q;
	input [44:0] l2_feq6_addr_q;
	input [44:0] l2_feq7_addr_q;
	input [44:0] l2_feq8_addr_q;
	input [44:0] l2_feq9_addr_q;
	input [44:0] l2_feq10_addr_q;
	input [44:0] l2_feq11_addr_q;
	input [44:0] l2_feq12_addr_q;
	input [44:0] l2_feq13_addr_q;
	input [44:0] l2_feq14_addr_q;
	input [44:0] l2_feq15_addr_q;

	`ifndef MAIA

	`ifdef FEQ20
	input [44:0] l2_feq16_addr_q;
	input [44:0] l2_feq17_addr_q;
	input [44:0] l2_feq18_addr_q;
	input [44:0] l2_feq19_addr_q;
	`endif

	`else

	input [44:0] l2_feq16_addr_q;
	input [44:0] l2_feq17_addr_q;
	input [44:0] l2_feq18_addr_q;
	input [44:0] l2_feq19_addr_q;
	input [44:0] l2_feq20_addr_q;
	input [44:0] l2_feq21_addr_q;
	input [44:0] l2_feq22_addr_q;
	input [44:0] l2_feq23_addr_q;
	`endif

	
	`else

	//L2 ASQ
	input        l2_bvalid_q;
	input [1:0]  l2_bresp_q;

	`ifndef MAIA
	input [5:0]  l2_bid_q;
	`else

	input [6:0]  l2_bid_q;
	`endif

	input [15:0] l2_asq_bid_match;
	input [44:0] l2_asq0_addr_q;
	input [44:0] l2_asq1_addr_q;
	input [44:0] l2_asq2_addr_q;
	input [44:0] l2_asq3_addr_q;
	input [44:0] l2_asq4_addr_q;
	input [44:0] l2_asq5_addr_q;
	input [44:0] l2_asq6_addr_q;
	input [44:0] l2_asq7_addr_q;
	input [44:0] l2_asq8_addr_q;
	input [44:0] l2_asq9_addr_q;
	input [44:0] l2_asq10_addr_q;
	input [44:0] l2_asq11_addr_q;
	input [44:0] l2_asq12_addr_q;
	input [44:0] l2_asq13_addr_q;
	input [44:0] l2_asq14_addr_q;
	input [44:0] l2_asq15_addr_q;
	`endif//}

	
	// arm register file
	input [31:0]	arm_rf_data00b0_q;
	input [31:0]	arm_rf_data01b0_q;
	input [31:0]	arm_rf_data02b0_q;
	input [31:0]	arm_rf_data03b0_q;
	input [31:0]	arm_rf_data04b0_q;
	input [31:0]	arm_rf_data05b0_q;
	input [31:0]	arm_rf_data06b0_q;
	input [31:0]	arm_rf_data07b0_q;
	input [31:0]	arm_rf_data08b0_q;
	input [31:0]	arm_rf_data09b0_q;
	input [31:0]	arm_rf_data10b0_q;
	input [31:0]	arm_rf_data11b0_q;
	input [31:0]	arm_rf_data12b0_q;
	input [31:0]	arm_rf_data13b0_q;
	input [31:0]	arm_rf_data14b0_q;
	input [31:0]	arm_rf_data15b0_q;
	input [31:0]	arm_rf_data16b0_q;
	input [31:0]	arm_rf_data17b0_q;
	input [31:0]	arm_rf_data18b0_q;
	input [31:0]	arm_rf_data19b0_q;
	input [31:0]	arm_rf_data20b0_q;
	input [31:0]	arm_rf_data21b0_q;
	input [31:0]	arm_rf_data22b0_q;
	input [31:0]	arm_rf_data23b0_q;
	input [31:0]	arm_rf_data24b0_q;
	input [31:0]	arm_rf_data25b0_q;
	input [31:0]	arm_rf_data26b0_q;
	input [31:0]	arm_rf_data27b0_q;
	input [31:0]	arm_rf_data28b0_q;
	input [31:0]	arm_rf_data29b0_q;
	input [31:0]	arm_rf_data30b0_q;
	input [31:0]	arm_rf_data31b0_q;
	input [31:0]	arm_rf_data32b0_q;
	input [31:0]	arm_rf_data33b0_q;
	input [31:0]	arm_rf_data34b0_q;
	input [31:0]	arm_rf_data35b0_q;
	input [31:0]	arm_rf_data36b0_q;
	input [31:0]	arm_rf_data37b0_q;
	input [31:0]	arm_rf_data38b0_q;
	input [31:0]	arm_rf_data39b0_q;
	input [31:0]	arm_rf_data40b0_q;
	input [31:0]	arm_rf_data41b0_q;
	
	input [31:0]	arm_rf_data00b1_q;
	input [31:0]	arm_rf_data01b1_q;
	input [31:0]	arm_rf_data02b1_q;
	input [31:0]	arm_rf_data03b1_q;
	input [31:0]	arm_rf_data04b1_q;
	input [31:0]	arm_rf_data05b1_q;
	input [31:0]	arm_rf_data06b1_q;
	input [31:0]	arm_rf_data07b1_q;
	input [31:0]	arm_rf_data08b1_q;
	input [31:0]	arm_rf_data09b1_q;
	input [31:0]	arm_rf_data10b1_q;
	input [31:0]	arm_rf_data11b1_q;
	input [31:0]	arm_rf_data12b1_q;
	input [31:0]	arm_rf_data13b1_q;
	input [31:0]	arm_rf_data14b1_q;
	input [31:0]	arm_rf_data15b1_q;
	input [31:0]	arm_rf_data16b1_q;
	input [31:0]	arm_rf_data17b1_q;
	input [31:0]	arm_rf_data18b1_q;
	input [31:0]	arm_rf_data19b1_q;
	input [31:0]	arm_rf_data20b1_q;
	input [31:0]	arm_rf_data21b1_q;
	input [31:0]	arm_rf_data22b1_q;
	input [31:0]	arm_rf_data23b1_q;
	input [31:0]	arm_rf_data24b1_q;
	input [31:0]	arm_rf_data25b1_q;
	input [31:0]	arm_rf_data26b1_q;
	input [31:0]	arm_rf_data27b1_q;
	input [31:0]	arm_rf_data28b1_q;
	input [31:0]	arm_rf_data29b1_q;
	input [31:0]	arm_rf_data30b1_q;
	input [31:0]	arm_rf_data31b1_q;
	input [31:0]	arm_rf_data32b1_q;
	input [31:0]	arm_rf_data33b1_q;
	input [31:0]	arm_rf_data34b1_q;
	input [31:0]	arm_rf_data35b1_q;
	input [31:0]	arm_rf_data36b1_q;
	input [31:0]	arm_rf_data37b1_q;
	input [31:0]	arm_rf_data38b1_q;
	input [31:0]	arm_rf_data39b1_q;
	input [31:0]	arm_rf_data40b1_q;
	input [31:0]	arm_rf_data41b1_q;
	
	// extension register file
	input [31:0]	ext_rf_data00_b0_q;
	input [31:0]	ext_rf_data00_b1_q;
	input [31:0]	ext_rf_data01_b0_q;
	input [31:0]	ext_rf_data01_b1_q;
	input [31:0]	ext_rf_data02_b0_q;
	input [31:0]	ext_rf_data02_b1_q;
	input [31:0]	ext_rf_data03_b0_q;
	input [31:0]	ext_rf_data03_b1_q;
	input [31:0]	ext_rf_data04_b0_q;
	input [31:0]	ext_rf_data04_b1_q;
	input [31:0]	ext_rf_data05_b0_q;
	input [31:0]	ext_rf_data05_b1_q;
	input [31:0]	ext_rf_data06_b0_q;
	input [31:0]	ext_rf_data06_b1_q;
	input [31:0]	ext_rf_data07_b0_q;
	input [31:0]	ext_rf_data07_b1_q;
	input [31:0]	ext_rf_data08_b0_q;
	input [31:0]	ext_rf_data08_b1_q;
	input [31:0]	ext_rf_data09_b0_q;
	input [31:0]	ext_rf_data09_b1_q;
	input [31:0]	ext_rf_data10_b0_q;
	input [31:0]	ext_rf_data10_b1_q;
	input [31:0]	ext_rf_data11_b0_q;
	input [31:0]	ext_rf_data11_b1_q;
	input [31:0]	ext_rf_data12_b0_q;
	input [31:0]	ext_rf_data12_b1_q;
	input [31:0]	ext_rf_data13_b0_q;
	input [31:0]	ext_rf_data13_b1_q;
	input [31:0]	ext_rf_data14_b0_q;
	input [31:0]	ext_rf_data14_b1_q;
	input [31:0]	ext_rf_data15_b0_q;
	input [31:0]	ext_rf_data15_b1_q;
	input [31:0]	ext_rf_data16_b0_q;
	input [31:0]	ext_rf_data16_b1_q;
	input [31:0]	ext_rf_data17_b0_q;
	input [31:0]	ext_rf_data17_b1_q;
	input [31:0]	ext_rf_data18_b0_q;
	input [31:0]	ext_rf_data18_b1_q;
	input [31:0]	ext_rf_data19_b0_q;
	input [31:0]	ext_rf_data19_b1_q;
	input [31:0]	ext_rf_data20_b0_q;
	input [31:0]	ext_rf_data20_b1_q;
	input [31:0]	ext_rf_data21_b0_q;
	input [31:0]	ext_rf_data21_b1_q;
	input [31:0]	ext_rf_data22_b0_q;
	input [31:0]	ext_rf_data22_b1_q;
	input [31:0]	ext_rf_data23_b0_q;
	input [31:0]	ext_rf_data23_b1_q;
	input [31:0]	ext_rf_data24_b0_q;
	input [31:0]	ext_rf_data24_b1_q;
	input [31:0]	ext_rf_data25_b0_q;
	input [31:0]	ext_rf_data25_b1_q;
	input [31:0]	ext_rf_data26_b0_q;
	input [31:0]	ext_rf_data26_b1_q;
	input [31:0]	ext_rf_data27_b0_q;
	input [31:0]	ext_rf_data27_b1_q;
	input [31:0]	ext_rf_data28_b0_q;
	input [31:0]	ext_rf_data28_b1_q;
	input [31:0]	ext_rf_data29_b0_q;
	input [31:0]	ext_rf_data29_b1_q;
	input [31:0]	ext_rf_data30_b0_q;
	input [31:0]	ext_rf_data30_b1_q;
	input [31:0]	ext_rf_data31_b0_q;
	input [31:0]	ext_rf_data31_b1_q;
	input [31:0]	ext_rf_data32_b0_q;
	input [31:0]	ext_rf_data32_b1_q;
	input [31:0]	ext_rf_data33_b0_q;
	input [31:0]	ext_rf_data33_b1_q;
	input [31:0]	ext_rf_data00_b2_q;
	input [31:0]	ext_rf_data00_b3_q;
	input [31:0]	ext_rf_data01_b2_q;
	input [31:0]	ext_rf_data01_b3_q;
	input [31:0]	ext_rf_data02_b2_q;
	input [31:0]	ext_rf_data02_b3_q;
	input [31:0]	ext_rf_data03_b2_q;
	input [31:0]	ext_rf_data03_b3_q;
	input [31:0]	ext_rf_data04_b2_q;
	input [31:0]	ext_rf_data04_b3_q;
	input [31:0]	ext_rf_data05_b2_q;
	input [31:0]	ext_rf_data05_b3_q;
	input [31:0]	ext_rf_data06_b2_q;
	input [31:0]	ext_rf_data06_b3_q;
	input [31:0]	ext_rf_data07_b2_q;
	input [31:0]	ext_rf_data07_b3_q;
	input [31:0]	ext_rf_data08_b2_q;
	input [31:0]	ext_rf_data08_b3_q;
	input [31:0]	ext_rf_data09_b2_q;
	input [31:0]	ext_rf_data09_b3_q;
	input [31:0]	ext_rf_data10_b2_q;
	input [31:0]	ext_rf_data10_b3_q;
	input [31:0]	ext_rf_data11_b2_q;
	input [31:0]	ext_rf_data11_b3_q;
	input [31:0]	ext_rf_data12_b2_q;
	input [31:0]	ext_rf_data12_b3_q;
	input [31:0]	ext_rf_data13_b2_q;
	input [31:0]	ext_rf_data13_b3_q;
	input [31:0]	ext_rf_data14_b2_q;
	input [31:0]	ext_rf_data14_b3_q;
	input [31:0]	ext_rf_data15_b2_q;
	input [31:0]	ext_rf_data15_b3_q;
	input [31:0]	ext_rf_data16_b2_q;
	input [31:0]	ext_rf_data16_b3_q;
	input [31:0]	ext_rf_data17_b2_q;
	input [31:0]	ext_rf_data17_b3_q;
	input [31:0]	ext_rf_data18_b2_q;
	input [31:0]	ext_rf_data18_b3_q;
	input [31:0]	ext_rf_data19_b2_q;
	input [31:0]	ext_rf_data19_b3_q;
	input [31:0]	ext_rf_data20_b2_q;
	input [31:0]	ext_rf_data20_b3_q;
	input [31:0]	ext_rf_data21_b2_q;
	input [31:0]	ext_rf_data21_b3_q;
	input [31:0]	ext_rf_data22_b2_q;
	input [31:0]	ext_rf_data22_b3_q;
	input [31:0]	ext_rf_data23_b2_q;
	input [31:0]	ext_rf_data23_b3_q;
	input [31:0]	ext_rf_data24_b2_q;
	input [31:0]	ext_rf_data24_b3_q;
	input [31:0]	ext_rf_data25_b2_q;
	input [31:0]	ext_rf_data25_b3_q;
	input [31:0]	ext_rf_data26_b2_q;
	input [31:0]	ext_rf_data26_b3_q;
	input [31:0]	ext_rf_data27_b2_q;
	input [31:0]	ext_rf_data27_b3_q;
	input [31:0]	ext_rf_data28_b2_q;
	input [31:0]	ext_rf_data28_b3_q;
	input [31:0]	ext_rf_data29_b2_q;
	input [31:0]	ext_rf_data29_b3_q;
	input [31:0]	ext_rf_data30_b2_q;
	input [31:0]	ext_rf_data30_b3_q;
	input [31:0]	ext_rf_data31_b2_q;
	input [31:0]	ext_rf_data31_b3_q;
	input [31:0]	ext_rf_data32_b2_q;
	input [31:0]	ext_rf_data32_b3_q;
	input [31:0]	ext_rf_data33_b2_q;
	input [31:0]	ext_rf_data33_b3_q;
	
	// psr register file
	input [4:0]	psr_rf_data00_q;
	input [4:0]	psr_rf_data01_q;
	input [4:0]	psr_rf_data02_q;
	input [4:0]	psr_rf_data03_q;
	
	input [31:0]  cpsr32;
	input [31:0]  cpsr64;
	input         dsu_aarch64_state;
	input         dsu_flush_trgt_aarch64;
	input [31:0]  fpexc;
	input [31:0]  fpscr;
	input [31:0]  dspsr;
	input [31:0]  mvfr0;
	input [31:0]  mvfr1;
	input [31:0]  mvfr2;
	input [31:0]  dec_aa64pfr0_el1;
	input [31:0]  dec_aa64pfr1_el1;
	input [31:0]  dec_aa64dfr0_el1;
	input [31:0]  dec_aa64dfr1_el1;
	input [31:0]  dec_aa64afr0_el1;
	input [31:0]  dec_aa64afr1_el1;
	input [31:0]  dec_aa64isar0_el1;
	input [31:0]  dec_aa64isar1_el1;
	input [31:0]  dec_aa64mmfr0_el1;
	input [31:0]  dec_aa64mmfr1_el1;
	input [31:0]  fpsid;
	input [31:0]  spsr_el1;
	input [31:0]  spsr_el2;
	input [31:0]  spsr_el3;
	input [31:0]  spsr_svc;
	input [31:0]  spsr_mon;
	input [31:0]  spsr_abt;
	input [31:0]  spsr_und;
	input [31:0]  spsr_irq;
	input [31:0]  spsr_fiq;
	input [31:0]  spsr_hyp;
	
	input        sp_uop_vld_i1;
	input        sp_uop_ns_i1;
	input [37:0] sp_uop_ctl_i1;
	input [63:0] sp_uop_wdata_i1;
	input        sp_resolved_ccpass_i1;
	input        sp_sync_done_i1;
	
	input        sp_uop_vld_p3;
	input [6:0]  sp_uop_gid_p3;
	input        sp_wfi_p3_q;
	input        sp_wfe_p3_q;
	input        wfi_wakeup_active;
	input        wfe_wakeup_active;
	
	// core tb inputs for va

	`ifdef CORE_TESTBENCH//{
	input         tb_lsu_ld_j;
	input [63:0]  tb_lsu_ld_va_j;
	input [ 6:0]  tb_lsu_ld_tag_j;
	input         tb_lsu_ld_k;
	input [63:0]  tb_lsu_ld_va_k;
	input [ 6:0]  tb_lsu_ld_tag_k;
	`endif//} // CORE_TESTBENCH

	
	wire  [9:0]       uop_cid_0p2_q;
	wire  [9:0]       uop_cid_1p2_q;
	wire  [9:0]       uop_cid_2p2_q;
	
	assign uop_cid_0p2_q[9:0] = {ls1_uop_vld_0p2_q,
		mx1_uop_vld_0p2_q,
		cx1_uop_vld_0p2_q,
		sxk_uop_vld_0p2_q,
		spr_uop_vld_0p2_q,
		bx_uop_vld_0p2_q,
		ls0_uop_vld_0p2_q,
		mx0_uop_vld_0p2_q,
		cx0_uop_vld_0p2_q,
		sxj_uop_vld_0p2_q};
	
	assign uop_cid_1p2_q[9:0] = {ls1_uop_vld_1p2_q,
		mx1_uop_vld_1p2_q,
		cx1_uop_vld_1p2_q,
		sxk_uop_vld_1p2_q,
		spr_uop_vld_1p2_q,
		bx_uop_vld_1p2_q,
		ls0_uop_vld_1p2_q,
		mx0_uop_vld_1p2_q,
		cx0_uop_vld_1p2_q,
		sxj_uop_vld_1p2_q};
	
	assign uop_cid_2p2_q[9:0] = {ls1_uop_vld_2p2_q,
		mx1_uop_vld_2p2_q,
		cx1_uop_vld_2p2_q,
		sxk_uop_vld_2p2_q,
		spr_uop_vld_2p2_q,
		bx_uop_vld_2p2_q,
		ls0_uop_vld_2p2_q,
		mx0_uop_vld_2p2_q,
		cx0_uop_vld_2p2_q,
		sxj_uop_vld_2p2_q};
	
	
	////////////////////////////////////////////////////////////////////////////
	//clusterID handling: select between the initial or dynamic-changed values//
	////////////////////////////////////////////////////////////////////////////
	`define PINS_CLUSTERID(X) ((X & 8'hff)    )
	`define PINS_CFGTE(X)     ((X & 1'b1) << 8)
	`define PINS_VINITHI(X)   ((X & 1'b1) << 9)
	`define PINS_CFGEND(X)    ((X & 1'b1) << 10)
	`define PINS_IMINLN(X)    ((X & 1'b1) << 11)
	`define PINS_CORENUM(X)   ((X & 2'b11) << 12)
	`define PINS_OLDCLID(X)   ((X & 8'hff) << 14)
	
	reg   reset_flopped;
	
	int pins_on_reset;
	int periphbase_39_8;
	reg [7:0] clusterid;		//must be a 8-bit reg for OPC_SEND() packet
	int clusterid_flopped;
	
	initial begin		//{Flop the clusterid in case the test reset it to other values so ISSCMP will create new TNC and delete the old(clusterid_flopped) one
		clusterid_flopped = -1;
	end		//}
	
	always@(posedge ck_gclkcr) begin
		reset_flopped <= `PRJ_DFF_DELAY reset;
		
		if(reset_flopped==1'b1 && reset==1'b0) begin
			pins_on_reset = 0;
			periphbase_39_8 = {periphbase[39:15],7'b000_0000};
			pins_on_reset += `PINS_CLUSTERID(clusterid_init[7:0]);
			pins_on_reset += `PINS_CFGTE(cfgte);
			pins_on_reset += `PINS_VINITHI(vinithi);
			pins_on_reset += `PINS_CFGEND(cfgend);
			pins_on_reset += `PINS_IMINLN(iminln);
			pins_on_reset += `PINS_CORENUM(`PRJ_CN);		//Number of Core
			pins_on_reset += `PINS_OLDCLID(clusterid_flopped);		//The clusterid before this reset
			
			reset_cpu(cpuid, pins_on_reset,periphbase_39_8);
			clusterid_flopped <= `PRJ_DFF_DELAY clusterid_init[7:0];
		end
	end
	
	always@(clusterid_flopped or clusterid_init) begin
		if(clusterid_flopped == -1) begin
			clusterid = clusterid_init;		//Cold Reset case
		end else if(clusterid_flopped === clusterid_init) begin
			clusterid = clusterid_init;		//Warm Reset case and reset_cpu() has been called to upate ISSCMP TraceAndCompare List with new ClusterID
		end else begin
			clusterid = clusterid_flopped;		//Warm Reset case before calling reset_cpu()
		end
	end
	///////////////////////////////////////////////////////////////////////
	//SP UOP Information for CPSR and other SP Registers                 //
	///////////////////////////////////////////////////////////////////////
	reg         sp_uop_ns_e1;
	reg         sp_uop_ns_e2;
	reg         sp_uop_vld_e1;
	reg [37:0]  sp_uop_ctl_e1;
	reg [63:0]  sp_uop_wdata_e1;
	reg         sp_ccfail_e1;
	reg         sp_uop_vld_e2;
	reg [37:0]  sp_uop_ctl_e2;
	reg [63:0]  sp_uop_wdata_e2;
	reg [63:0]  sp_uop_data_e2;
	reg         sp_ccfail_e2;
	reg         waiting_for_sync_done;		//Need to move all signals declaration to the top to avoid dependency
	reg         switch_mode_32To64;
	reg         init_aarch64;
	wire [31:0] cpsr;
	wire [31:0] actlr;
	
	
	
	wire	[31:0]	csselr;
	wire	[31:0]	sctlr;
	wire	[31:0]	ttbr0_hi;
	wire	[31:0]	ttbr0_lo;
	wire	[31:0]	ttbr1_hi;
	wire	[31:0]	ttbr1_lo;
	wire	[31:0]	ttbcr;
	wire	[31:0]	dacr;
	wire	[31:0]	dfsr;
	wire	[31:0]	ifsr;
	wire	[31:0]	adfsr;
	wire	[31:0]	aifsr;
	wire	[31:0]	dfar;
	wire	[31:0]	ifar;
	wire	[31:0]	prrr_mair0;
	wire	[31:0]	nmrr_mair1;
	wire	[31:0]	amair0;
	wire	[31:0]	amair1;
	wire	[31:0]	vbar;
	wire	[31:0]	contextidr;
	wire	[31:0]	tpidrurw;
	wire	[31:0]	tpidruro;
	wire	[31:0]	tpidrprw;
	
	
	assign csselr = sp_uop_ns_e2 ? csselr_ns : csselr_s;
	assign sctlr = sp_uop_ns_e2 ? sctlr_ns : sctlr_s;
	assign actlr = sp_uop_ns_e2 ? actlr_ns : actlr_s;
	assign ttbr0_hi = sp_uop_ns_e2 ? ttbr0_hi_ns : ttbr0_hi_s;
	assign ttbr0_lo = sp_uop_ns_e2 ? ttbr0_lo_ns : ttbr0_lo_s;
	assign ttbr1_hi = sp_uop_ns_e2 ? ttbr1_hi_ns : ttbr1_hi_s;
	assign ttbr1_lo = sp_uop_ns_e2 ? ttbr1_lo_ns : ttbr1_lo_s;
	assign ttbcr = sp_uop_ns_e2 ? ttbcr_ns : ttbcr_s;
	assign dacr = sp_uop_ns_e2 ? dacr_ns : dacr_s;
	assign dfsr = sp_uop_ns_e2 ? dfsr_ns : dfsr_s;
	assign ifsr = sp_uop_ns_e2 ? ifsr_ns : ifsr_s;
	assign adfsr = sp_uop_ns_e2 ? adfsr_ns : adfsr_s;
	assign aifsr = sp_uop_ns_e2 ? aifsr_ns : aifsr_s;
	assign dfar = sp_uop_ns_e2 ? dfar_ns : dfar_s;
	assign ifar = sp_uop_ns_e2 ? ifar_ns : ifar_s;
	assign prrr_mair0 = sp_uop_ns_e2 ? prrr_mair0_ns : prrr_mair0_s;
	assign nmrr_mair1 = sp_uop_ns_e2 ? nmrr_mair1_ns : nmrr_mair1_s;
	assign amair0 = sp_uop_ns_e2 ? amair0_ns : amair0_s;
	assign amair1 = sp_uop_ns_e2 ? amair1_ns : amair1_s;
	assign vbar = sp_uop_ns_e2 ? vbar_ns : vbar_s;
	assign contextidr = sp_uop_ns_e2 ? contextidr_ns : contextidr_s;
	assign tpidrurw = sp_uop_ns_e2 ? tpidrurw_ns : tpidrurw_s;
	assign tpidruro = sp_uop_ns_e2 ? tpidruro_ns : tpidruro_s;
	assign tpidrprw = sp_uop_ns_e2 ? tpidrprw_ns : tpidrprw_s;
	
	
	
	always@(posedge ck_gclkcr) begin
		if(reset) begin
			sp_uop_vld_e1 <= `PRJ_DFF_DELAY 1'b0;
			sp_uop_vld_e2 <= `PRJ_DFF_DELAY 1'b0;
		end
		else begin
			sp_uop_vld_e1       <= `PRJ_DFF_DELAY sp_uop_vld_i1;
			sp_uop_ns_e1        <= `PRJ_DFF_DELAY sp_uop_ns_i1;
			sp_uop_ctl_e1[37:0] <= `PRJ_DFF_DELAY sp_uop_ctl_i1[37:0];
			sp_uop_wdata_e1[63:0] <= `PRJ_DFF_DELAY sp_uop_wdata_i1[63:0];
			sp_ccfail_e1        <= `PRJ_DFF_DELAY ~sp_resolved_ccpass_i1;
			
			sp_uop_vld_e2       <= `PRJ_DFF_DELAY sp_uop_vld_e1;
			sp_uop_ns_e2        <= `PRJ_DFF_DELAY sp_uop_ns_e1;
			sp_uop_ctl_e2[37:0] <= `PRJ_DFF_DELAY sp_uop_ctl_e1[37:0];
			sp_uop_wdata_e2[63:0] <= `PRJ_DFF_DELAY sp_uop_wdata_e1[63:0];
			sp_ccfail_e2        <= `PRJ_DFF_DELAY sp_ccfail_e1;
		end
	end
	
	initial begin
		init_aarch64 = 1'b0;

		`ifndef DSM_MODEL//{

		`ifdef CORE_TESTBENCH//{
		if($test$plusargs("r_aarch64")) begin
			init_aarch64 = 1'b1;
		end
		`else

		if($test$plusargs("arch64")) begin
			init_aarch64 = 1'b1;
		end
		`endif//}

		`endif//}   // ifndef DSM_MODEL

	end
	
	assign cpsr = dsu_aarch64_state ? cpsr64 : cpsr32;
	
	// NOTE: sp_uop_ctl_e2[34] is uop_ctl_p2[55]. This is remapped in SP_RF
	// GIC Remote                                                        sp_uop_ctl_e2[37]
	// RZW: RAZ/WI, read as zero, write ignore                           sp_uop_ctl_e2[36] <--- For Unpred case of MSR/MCR, need to drop the write
	// ExO: executing in postamble                                       sp_uop_ctl_e2[35]
	// A64                                                               sp_uop_ctl_e2[34]
	// Remote                                                            sp_uop_ctl_e2[33]
	// Remote Interface: DT, IF, LS, L2                                  sp_uop_ctl_e2[32:29]
	// Remote Addr                                                       sp_uop_ctl_e2[28:22]
	// ExR: executing in preamble                                        sp_uop_ctl_e2[21]
	// CMR                                                               sp_uop_ctl_e2[20]
	// Rd : always Rd even if ccfail (must return some data to MX uop)   sp_uop_ctl_e2[19]
	// Wr : squish Wr if ccfail                                          sp_uop_ctl_e2[18]
	// Addr                                                              sp_uop_ctl_e2[17:0]
	// sp_uop_ctl_e2[34],sp_uop_ctl_e2[17:16] == 3'b010)  // AArch32 cp14  MCRR/MRRC
	// sp_uop_ctl_e2[34],sp_uop_ctl_e2[17:16] == 3'b011)  // AArch32 cp15  MCRR/MRRC
	// sp_uop_ctl_e2[34],sp_uop_ctl_e2[17:15] == 4'b1000) // AArch64 other MSR/MRS
	// sp_uop_ctl_e2[34],sp_uop_ctl_e2[17:15] == 4'b1010) // AArch64 cp14  MSR/MRS
	// sp_uop_ctl_e2[34],sp_uop_ctl_e2[17:15] == 4'b1011) // AArch64 cp15  MSR/MRS
	
	always @(*) begin
		casez(sp_uop_ctl_e2[32:0])
				//=================================================================================================================//
				// Remote Registers
				33'b1_0001_????_????_????_????_????_????_???? : sp_uop_data_e2[63:0] = l2_spr_wr_data_e2_q[63:0];
			33'b1_0010_????_????_????_????_????_????_???? : sp_uop_data_e2[63:0] = ls_spr_wr_data_e2_q[63:0];
			33'b1_0100_????_????_????_????_????_????_???? : sp_uop_data_e2[63:0] = if_spr_wr_data_e2_q[63:0];
			33'b1_1000_????_????_????_????_????_????_???? : sp_uop_data_e2[63:0] = dt_spr_wr_data_e2_q[63:0];
			
			//=================================================================================================================//
			//DS Local CP15R
			33'b0_????_????_????_??01_0000_0110_000?_0000 : sp_uop_data_e2[63:0] = {32'h0,teecr[31:0]};
			33'b0_????_????_????_??01_0000_1110_000?_0000 : sp_uop_data_e2[63:0] = {32'h0,teehbr[31:0]};
			
			//=================================================================================================================//
			//DS Local CP15R
			//CRn=0,    CRn  op1 op2   CRm
			33'b0_????_????_????_??011_0000_010_000_?_0000 : sp_uop_data_e2[63:0] = {32'h0,csselr[31:0]};
			33'b0_????_????_????_??011_0000_100_000_?_0000 : sp_uop_data_e2[63:0] = {32'h0,vpidr[31:0]};
			33'b0_????_????_????_??011_0000_100_101_?_0000 : sp_uop_data_e2[63:0] = {32'h0,vmpidr[31:0]};
			
			//=================================================================================================================//
			// CRn=1                   CRn  op1 op2   CRm
			33'b0_????_????_????_??011_0001_000_000_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ?  {32'h0,sctlr_ns[31:0]} : {32'h0,sctlr[31:0]};
			33'b0_????_????_????_??011_0001_000_001_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ?  {32'h0,actlr_ns[31:0]} : {32'h0,actlr[31:0]};
			33'b0_????_????_????_??011_0001_000_010_?_0000 : sp_uop_data_e2[63:0] = {32'h0,cpacr[31:0]};
			33'b0_????_????_????_??011_0001_000_000_?_0001 : sp_uop_data_e2[63:0] = {32'h0,scr[31:0]};
			33'b0_????_????_????_??011_0001_000_001_?_0001 : sp_uop_data_e2[63:0] = {32'h0,sder[31:0]};
			33'b0_????_????_????_??011_0001_000_010_?_0001 : sp_uop_data_e2[63:0] = {32'h0,nsacr[31:0]};
			33'b0_????_????_????_??011_0001_100_000_?_0000 : sp_uop_data_e2[63:0] = {32'h0,hsctlr[31:0]};
			//Note: hcr2,hcr is one 64-bit Register in ISSCMP and CTModel
			33'b0_????_????_????_??011_0001_100_000_?_0001 : sp_uop_data_e2[63:0] = {hcr2[31:0],hcr[31:0]};		//AArch64/32
			33'b0_????_????_????_??011_0001_100_100_?_0001 : sp_uop_data_e2[63:0] = {hcr2[31:0],hcr[31:0]};		//AArch32 Only
			33'b0_????_????_????_??011_0001_100_001_?_0000 : sp_uop_data_e2[63:0] = {32'h0,hactlr[31:0]};
			33'b0_????_????_????_??011_0001_100_001_?_0001 : sp_uop_data_e2[63:0] = {32'h0,hdcr[31:0]};
			33'b0_????_????_????_??011_0001_100_010_?_0001 : sp_uop_data_e2[63:0] = {32'h0,hcptr[31:0]};
			33'b0_????_????_????_??011_0001_100_011_?_0001 : sp_uop_data_e2[63:0] = {32'h0,hstr[31:0]};
			33'b0_????_????_????_??011_0001_100_111_?_0001 : sp_uop_data_e2[63:0] = {32'h0,hacr[31:0]};
			//Those are AArch64 only
			33'b0_????_????_????_??011_0001_110_000_?_0000 : sp_uop_data_e2[63:0] = {32'h0,sctlr_s[31:0]};		//SCTLR_EL3
			33'b0_????_????_????_??011_0001_110_001_?_0000 : sp_uop_data_e2[63:0] = {32'h0,actlr_s[31:0]};		//ACTLR_EL3
			33'b0_????_????_????_??011_0001_110_000_?_0001 : sp_uop_data_e2[63:0] = {32'h0,scr[31:0]};		//SCR_EL3
			33'b0_????_????_????_??011_0001_110_001_?_0001 : sp_uop_data_e2[63:0] = {32'h0,sder[31:0]};		//SDER32_EL3
			33'b0_????_????_????_??011_0001_110_010_?_0001 : sp_uop_data_e2[63:0] = {32'h0,cptr_el3[31:0]};		//CPTR_EL3
			33'b0_????_????_????_??011_0001_110_001_?_0011 : sp_uop_data_e2[63:0] = {32'h0,mdcr_el3[31:0]};		//MDCR_EL3
			//Those are AArch32 only
			33'b0_????_????_????_??011_0001_000_001_?_0011 : sp_uop_data_e2[63:0] = {32'h0,mdcr_el3[31:0]};		//SDCR
			
			//=================================================================================================================//
			// CRn=2                   CRn  op1 op2   CRm
			//Special care needed to distinguish 32-bit vs 64-bit Write
			//DS Local CP15SS          CRn  op1 op2   CRm
			33'b0_????_????_????_??011_0010_000_000_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {ttbr0_hi_ns[31:0],ttbr0_lo_ns[31:0]} : {32'h0,ttbr0_lo[31:0]};
			33'b0_????_????_????_??011_0010_000_001_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {ttbr1_hi_ns[31:0],ttbr1_lo_ns[31:0]} : {32'h0,ttbr1_lo[31:0]};
			33'b0_????_????_????_??011_0010_000_010_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {tcr_el1[63:0]} : {32'h0,ttbcr[31:0]};
			
			33'b0_????_????_????_??011_0010_100_010_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {tcr_el2[63:0]} : {32'h0,htcr[31:0]};
			33'b0_????_????_????_??011_0010_100_010_?_0001 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {vtcr_el2[63:0]} : {32'h0,vtcr[31:0]};
			
			//Those are AArch64 only
			33'b0_????_????_????_??011_0010_100_000_?_0000 : sp_uop_data_e2[63:0] = {httbr_hi[31:0],httbr_lo[31:0]};		//AArch64 Only
			33'b0_????_????_????_??011_0010_100_000_?_0001 : sp_uop_data_e2[63:0] = {vttbr_hi[31:0],vttbr_lo[31:0]};		//AArch64 Only
			33'b0_????_????_????_??011_0010_110_000_?_0000 : sp_uop_data_e2[63:0] = {ttbr0_hi_s[31:0],ttbr0_lo_s[31:0]};		//AArch64 Only
			33'b0_????_????_????_??011_0010_110_010_?_0000 : sp_uop_data_e2[63:0] = {tcr_el3[63:0]};		//AArch64 Only
			
			//=================================================================================================================//
			// CRn=3                   CRn  op1 op2   CRm
			33'b0_????_????_????_??011_0011_000_000_?_0000 : sp_uop_data_e2[31:0] = {32'h0,dacr[31:0]};		//AArch32 Only
			//AArch64 Write
			33'b0_????_????_????_??011_0011_100_000_?_0000 : sp_uop_data_e2[63:0] = {32'h0,dacr_ns[31:0]};		//AArch64 Only
			
			//=================================================================================================================//
			// CRn=4                   CRn  op1 op2   CRm
			//***This is New and AArch64 Only through MSR***
			33'b0_????_????_????_??011_0100_000_001_?_0000 : sp_uop_data_e2[31:0] = {arm_rf_data36b1_q,arm_rf_data36b0_q};		//ELR_EL1
			33'b0_????_????_????_??011_0100_100_001_?_0000 : sp_uop_data_e2[31:0] = {arm_rf_data34b1_q,arm_rf_data34b0_q};		//ELR_EL2
			33'b0_????_????_????_??011_0100_110_001_?_0000 : sp_uop_data_e2[31:0] = {arm_rf_data32b1_q,arm_rf_data32b0_q};		//ELR_EL3
			33'b0_????_????_????_??011_0100_000_000_?_0001 : sp_uop_data_e2[31:0] = {arm_rf_data39b1_q,arm_rf_data39b0_q};		//SP_EL0
			33'b0_????_????_????_??011_0100_100_000_?_0001 : sp_uop_data_e2[31:0] = {arm_rf_data37b1_q,arm_rf_data37b0_q};		//SP_EL1
			33'b0_????_????_????_??011_0100_110_000_?_0001 : sp_uop_data_e2[31:0] = {arm_rf_data35b1_q,arm_rf_data35b0_q};		//SP_EL2
			33'b0_????_????_????_??011_0100_011_001_?_0101 : sp_uop_data_e2[63:0] = {arm_rf_data38b1_q,arm_rf_data38b0_q};		//DLR
			
			//=================================================================================================================//
			// CRn=5                   CRn  op1 op2   CRm
			33'b0_????_????_????_??011_0101_000_000_?_0000 : sp_uop_data_e2[63:0] = {32'h0,dfsr[31:0]};		//AArch32 Only
			33'b0_????_????_????_??011_0101_000_001_?_0000 : sp_uop_data_e2[63:0] = {32'h0,ifsr[31:0]};		//AArch32 Only
			
			33'b0_????_????_????_??011_0101_000_000_?_0001 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {32'h0,adfsr_ns[31:0]} : {32'h0,adfsr[31:0]};
			33'b0_????_????_????_??011_0101_000_001_?_0001 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {32'h0,aifsr_ns[31:0]} : {32'h0,adfsr[31:0]};
			
			33'b0_????_????_????_??011_0101_100_000_?_0001 : sp_uop_data_e2[63:0] = {32'h0,hadfsr[31:0]};
			33'b0_????_????_????_??011_0101_100_001_?_0001 : sp_uop_data_e2[63:0] = {32'h0,haifsr[31:0]};
			33'b0_????_????_????_??011_0101_100_000_?_0010 : sp_uop_data_e2[63:0] = {32'h0,hsr[31:0]};
			
			33'b0_????_????_????_??011_0101_100_001_?_0000 : sp_uop_data_e2[63:0] = {32'h0,ifsr_ns[31:0]};		//IFSR32_EL2
			33'b0_????_????_????_??011_0101_100_000_?_0011 : sp_uop_data_e2[63:0] = {32'h0,fpexc[31:0]};		//FPEXC32_EL2
			33'b0_????_????_????_??011_0101_100_000_?_0010 : sp_uop_data_e2[63:0] = {32'h0,hsr[31:0]};		//ESR_EL2
			
			//Those are AArch64 only
			33'b0_????_????_????_??011_0101_110_000_?_0001 : sp_uop_data_e2[63:0] = {32'h0,adfsr_s[31:0]};		//AFSR0_EL3
			33'b0_????_????_????_??011_0101_110_001_?_0001 : sp_uop_data_e2[63:0] = {32'h0,aifsr_s[31:0]};		//AFSR1_EL3
			33'b0_????_????_????_??011_0101_000_000_?_0010 : sp_uop_data_e2[63:0] = {32'h0,dfsr_ns[31:0]};		//ESR_EL1
			33'b0_????_????_????_??011_0101_110_000_?_0010 : sp_uop_data_e2[63:0] = {32'h0,dfsr_s[31:0]};		//ESR_EL3
			
			//=================================================================================================================//
			// CRn=6                   CRn  op1 op2   CRm
			//Special care needed to distinguish 32-bit vs 64-bit Write
			33'b0_????_????_????_??011_0110_000_010_?_0000 : sp_uop_data_e2[63:0] = {32'h0,ifar[31:0]};
			33'b0_????_????_????_??011_0110_100_010_?_0000 : sp_uop_data_e2[63:0] = {32'h0,hifar[31:0]};
			//AArch64 Write
			33'b0_????_????_????_??011_0110_000_000_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {ifar_ns[31:0],dfar_ns[31:0]} : {32'h0,dfar[31:0]};
			33'b0_????_????_????_??011_0110_100_000_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {hifar[31:0],hdfar[31:0]} : {32'h0,hdfar[31:0]};
			33'b0_????_????_????_??011_0110_100_100_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {hpfar_el2[63:0]} : {32'h0,hpfar[31:0]};
			33'b0_????_????_????_??011_0110_110_000_?_0000 : sp_uop_data_e2[63:0] = {far_el3[63:0]};
			
			//=================================================================================================================//
			// CRn=10                  CRn  op1 op2   CRm
			//Special care needed to distinguish 32-bit vs 64-bit Write
			33'b0_????_????_????_??011_1010_000_001_?_0010 : sp_uop_data_e2[63:0] = {32'h0,nmrr_mair1[31:0]};
			33'b0_????_????_????_??011_1010_000_001_?_0011 : sp_uop_data_e2[63:0] = {32'h0,amair1[31:0]};
			33'b0_????_????_????_??011_1010_100_001_?_0010 : sp_uop_data_e2[63:0] = {32'h0,hmair1[31:0]};
			33'b0_????_????_????_??011_1010_100_001_?_0011 : sp_uop_data_e2[63:0] = {32'h0,hamair1[31:0]};
			
			33'b0_????_????_????_??011_1010_000_000_?_0010 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {nmrr_mair1_ns[31:0],prrr_mair0_ns[31:0]} : {32'h0,prrr_mair0[31:0]};
			33'b0_????_????_????_??011_1010_000_000_?_0011 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {amair1_ns[31:0],amair0_ns[31:0]} : {32'h0,amair0[31:0]};
			33'b0_????_????_????_??011_1010_100_000_?_0010 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {hmair1[31:0],hmair0[31:0]} : {32'h0,hmair0[31:0]};
			33'b0_????_????_????_??011_1010_100_000_?_0011 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {hamair1[31:0],hamair0[31:0]} : {32'h0,hamair0[31:0]};
			
			//Those are AArch64 only
			33'b0_????_????_????_??011_1010_110_000_?_0010 : sp_uop_data_e2[63:0] = {nmrr_mair1_s[31:0],prrr_mair0_s[31:0]};
			33'b0_????_????_????_??011_1010_110_000_?_0011 : sp_uop_data_e2[63:0] = {amair1_s[31:0],amair0_s[31:0]};
			//=================================================================================================================//
			// CRn=12                  CRn  op1 op2   CRm
			33'b0_????_????_????_??011_1100_000_001_?_0000 : sp_uop_data_e2[63:0] = {32'h0,mvbar[31:0]};		//AArch32 Only
			33'b0_????_????_????_??011_1100_000_010_?_0000 : sp_uop_data_e2[63:0] = {rmr_el3[63:0]};		//AArch32 MCR
			
			//AArch64 Write
			33'b0_????_????_????_??011_1100_000_000_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {vbar_el1[63:0]} : {32'h0,vbar[31:0]};
			33'b0_????_????_????_??011_1100_100_000_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? {vbar_el2[63:0]} : {32'h0,hvbar[31:0]};
			33'b0_????_????_????_??011_1100_000_000_?_0001 : sp_uop_data_e2[63:0] = {isr_el1[63:0]};
			
			//Those are AArch64 only
			33'b0_????_????_????_??011_1100_110_000_?_0000 : sp_uop_data_e2[63:0] = {vbar_el3[63:0]};
			33'b0_????_????_????_??011_1100_110_001_?_0000 : sp_uop_data_e2[63:0] = {rvbar_el3[63:0]};
			33'b0_????_????_????_??011_1100_110_010_?_0000 : sp_uop_data_e2[63:0] = {rmr_el3[63:0]};		//AArch64 MSR
			
			//=================================================================================================================//
			// CRn=13                  CRn  op1 op2   CRm
			33'b0_????_????_????_??011_1101_000_001_?_0000 : sp_uop_data_e2[63:0] = {32'h0,contextidr[31:0]};
			33'b0_????_????_????_??011_1101_000_000_?_0000 : sp_uop_data_e2[63:0] = {32'h0,fcseidr[31:0]};		//AArch32 Only
			33'b0_????_????_????_??011_1101_000_010_?_0000 : sp_uop_data_e2[63:0] = {32'h0,tpidrurw[31:0]};		//AArch32 Only
			33'b0_????_????_????_??011_1101_000_011_?_0000 : sp_uop_data_e2[63:0] = {32'h0,tpidruro[31:0]};		//AArch32 Only
			
			33'b0_????_????_????_??011_1101_000_100_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? tpidr_el1[63:0] : {32'h0,tpidrprw[31:0]};
			33'b0_????_????_????_??011_1101_100_010_?_0000 : sp_uop_data_e2[63:0] = dsu_aarch64_state ? tpidr_el2[63:0] : {32'h0,htpidr[31:0]};
			
			//Those are AArch64 only
			33'b0_????_????_????_??011_1101_011_010_?_0000 : sp_uop_data_e2[63:0] = {tpidr_el0[63:0]};
			33'b0_????_????_????_??011_1101_011_011_?_0000 : sp_uop_data_e2[63:0] = {tpidrro_el0[63:0]};
			33'b0_????_????_????_??011_1101_110_010_?_0000 : sp_uop_data_e2[63:0] = {tpidr_el3[63:0]};
			
			//=================================================================================================================//
			// AArch32 Local Others: CPSR/SPSR/FPxxx
			// [17:15]=0x0(Other)  PrimSpec[2:0]=[14:12]  SecSpec[4:0]=[8:4]
			33'b0_????_????_????_??_000_100_???_?????_???? : sp_uop_data_e2[63:0] = {32'h0,cpsr[31:0]};
			33'b0_????_????_????_??_000_110_???_10001_???? : sp_uop_data_e2[63:0] = {32'h0,spsr_fiq[31:0]};
			33'b0_????_????_????_??_000_110_???_10010_???? : sp_uop_data_e2[63:0] = {32'h0,spsr_irq[31:0]};
			33'b0_????_????_????_??_000_110_???_10011_???? : sp_uop_data_e2[63:0] = {32'h0,spsr_svc[31:0]};
			33'b0_????_????_????_??_000_110_???_10110_???? : sp_uop_data_e2[63:0] = {32'h0,spsr_mon[31:0]};
			33'b0_????_????_????_??_000_110_???_10111_???? : sp_uop_data_e2[63:0] = {32'h0,spsr_abt[31:0]};
			33'b0_????_????_????_??_000_110_???_11010_???? : sp_uop_data_e2[63:0] = {32'h0,spsr_hyp[31:0]};
			33'b0_????_????_????_??_000_110_???_11011_???? : sp_uop_data_e2[63:0] = {32'h0,spsr_und[31:0]};
			33'b0_????_????_????_??_000_000_????_????_0000 : sp_uop_data_e2[63:0] = {32'h0,fpsid[31:0]};
			33'b0_????_????_????_??_000_000_????_????_0001 : sp_uop_data_e2[63:0] = {32'h0,fpscr[31:0]};
			33'b0_????_????_????_??_000_000_????_????_0101 : sp_uop_data_e2[63:0] = {32'h0,mvfr2[31:0]};
			33'b0_????_????_????_??_000_000_????_????_0110 : sp_uop_data_e2[63:0] = {32'h0,mvfr1[31:0]};
			33'b0_????_????_????_??_000_000_????_????_0111 : sp_uop_data_e2[63:0] = {32'h0,mvfr0[31:0]};
			33'b0_????_????_????_??_000_000_????_????_1000 : sp_uop_data_e2[63:0] = {32'h0,fpexc[31:0]};
			
			// AArch64 Crn=4 Local Others FPxxx/CPSR/SPSR:NZCV-DAIF-SPSel-Mode
			// [17:15]=0x0(Other)  PrimSpec[2:0]=[14:12]  SecSpec[2:0]=[8:6]
			
			33'b0_????_????_????_??_000_110_???_001??_???? : sp_uop_data_e2[63:0] = {32'h0,spsr_el1[31:0]};
			33'b0_????_????_????_??_000_110_???_010??_???? : sp_uop_data_e2[63:0] = {32'h0,spsr_el2[31:0]};
			33'b0_????_????_????_??_000_110_???_011??_???? : sp_uop_data_e2[63:0] = {32'h0,spsr_el3[31:0]};
			
			33'b0_????_????_????_??_000_000_????_????_???? : sp_uop_data_e2[63:0] = {32'h0,fpscr[31:0]};		//FPCR and FPSR
			33'b0_????_????_????_??_000_101_????_????_???? : sp_uop_data_e2[63:0] = {32'h0,dspsr[31:0]};		//DSPSR
			//33'b0_????_????_????_??_000_111_????_????_???? : //SEV and SEVL
			
			//=================================================================================================================//
			//DS Local CP15RR         hi/lo     Op1  CRm
			//AArch32 Write
			33'b0_????_????_????_??11_?_???????_0000_0010 : sp_uop_data_e2[63:0] = {ttbr0_hi[31:0],ttbr0_lo[31:0]};
			33'b0_????_????_????_??11_?_???????_0001_0010 : sp_uop_data_e2[63:0] = {ttbr1_hi[31:0],ttbr1_lo[31:0]};
			33'b0_????_????_????_??11_?_???????_0100_0010 : sp_uop_data_e2[63:0] = {httbr_hi[31:0],httbr_lo[31:0]};
			33'b0_????_????_????_??11_?_???????_0110_0010 : sp_uop_data_e2[63:0] = {vttbr_hi[31:0],vttbr_lo[31:0]};
			33'b0_????_????_????_??11_1_???????_0000_1111 : sp_uop_data_e2[63:0] = {32'h0,cpuactlr_el1[31:0]};
			
			
			//=================================================================================================================//
			//New in AArch64
			33'b0_????_????_????_??011_1111_001_010_?_0000 : sp_uop_data_e2[63:0] = {32'h0,cpuactlr_el1[31:0]};
			
			//Other SP Registers
			default : sp_uop_data_e2 = sp_uop_wdata_e2;
		endcase
	end
	///////////////////////////////////////////////////////////////////////
	// Callbacks from the C++ world
	///////////////////////////////////////////////////////////////////////
	
	reg        isscmp_detected_end_of_test;
	reg        isscmp_mismatch;
	reg        isscmp_fatal;
	reg        isscmp_idle;
	reg        iss_nofail;
	

	`ifdef EAGLE_OPCODE_COVERAGE//{
	reg  [31:0] opc_opc;
	reg         opc_tbit;
	reg         opc_size;
	reg         opc_conditional;
	wire [5:0]  opc_lsm_regcnt;
	wire        opc_lsm_uop_cnt_1_at;
	wire        opc_lsm_uop_cnt_2_at;
	wire        opc_lsm_uop_cnt_1_neon;
	wire        opc_lsm_uop_cnt_2_neon;
	wire        opc_lsm_found;
	wire        opc_base_in_lsm;
	
	wire       opc_arm_cp_or_neon_inst;
	wire       opc_t2_cp_or_neon_inst;
	wire       opc_cp_or_neon_inst;
	assign     opc_cp_or_neon_inst = opc_tbit ? opc_t2_cp_or_neon_inst : opc_arm_cp_or_neon_inst;
	

	`ifdef MAIA
	maia_dec_ncdetect uncdetect_opc(
	`else

	xm_dec_ncdetect uncdetect_opc(
	`endif

	.inst_d1 (opc_opc[31:4]),
		// output
		.arm_cp_or_neon_inst_d1 (opc_arm_cp_or_neon_inst),
		.t2_cp_or_neon_inst_d1  (opc_t2_cp_or_neon_inst)
		);
	

	`ifdef MAIA
	maia_dec_lsm_regcnt_d1 ulsm_regcnt_opc(
	`else

	xm_dec_lsm_regcnt_d1 ulsm_regcnt_opc(
	`endif

	.ifu_inst_h_d1 (opc_opc[31:16]),
		.ifu_inst_l_d1 (opc_opc[15:0]),
		.tbit_d1      (opc_tbit),
		.size_d1      (opc_size),
		.conditional_d1(opc_conditional),
		.cp_or_neon_sel_d1(opc_cp_or_neon_inst),
		
		// output
		.lsm_regcnt_d1 (opc_lsm_regcnt),
		.lsm_uopcnt_1_at_d1 (opc_lsm_uopcnt_1_at),
		.lsm_uopcnt_2_at_d1 (opc_lsm_uopcnt_2_at),
		.lsm_uopcnt_1_neon_d1 (opc_lsm_uopcnt_1_neon),
		.lsm_uopcnt_2_neon_d1 (opc_lsm_uopcnt_2_neon),
		.lsm_found_d1         (opc_lsm_found),
		.base_in_lsm_d1       (opc_base_in_lsm)
		);
	
	xm_arm_opcode_coverage arm_opcode_coverage;
	xm_thumb_opcode_coverage thumb_opcode_coverage;
	xm_arm_neon_opcode_coverage arm_neon_opcode_coverage;
	xm_thumb_neon_opcode_coverage thumb_neon_opcode_coverage;
	xm_a64_opcode_coverage a64_opcode_coverage;
	reg mytbit;
	reg myccpass;
	reg mysize;
	reg mycp15sdisable;
	reg mysecure;
	initial begin
		arm_opcode_coverage = new();
		thumb_opcode_coverage = new();
		arm_neon_opcode_coverage = new();
		thumb_neon_opcode_coverage = new();
		a64_opcode_coverage = new();
	end
	
	export "DPI-C" function isscmp_opc_cov_callback_DPI;
	function void isscmp_opc_cov_callback_DPI(bit [31:0] myopcode,bit [31:0] mycpsr,bit [31:0] myscr,bit [31:0] mysctlrns,bit [31:0] mysctlrs,bit [63:0] myactlr,bit [31:0] myother);
		// myother: bit 3 == tbit, bit 2 == ccpass, bit 1 == size, bit 0 == cp15sdisable
		//$display("entered isscmp_opc_cov_callback_DPI\n");
		mytbit = myother[3];
		myccpass = myother[2];
		mysize = myother[1];
		mycp15sdisable = myother[0];
		mysecure = ~myscr[0] || (mycpsr[4:0]==5'h16);
		
		opc_opc = myopcode;
		opc_tbit = mytbit;
		opc_size = mysize;
		opc_conditional = 1'b0;
		
		//$display("OPC_COV: opcode: %8h, cpsr: %8h, scr: %8h, sctlr_ns: %8h, sctlr_s: %8h, actlr: %8h, other: %8h, tbit: %1b, ccpass: %1b, size: %1b, cp15sdisable: %1b\n",myopcode,mycpsr,myscr,mysctlrns,mysctlrs,myactlr,myother,mytbit,myccpass,mysize,mycp15sdisable);
		
		if (mycpsr[4]) begin
			if (!mytbit) begin
				arm_opcode_coverage.new_opcode(.orig_inst(myopcode),
					.cp15bar_en(1'b0),
					.secure(mysecure),
					.hypervisor(mycpsr[4:0]==5'h1a),
					.chickbit_wfinop(myactlr[8]),
					.user(mycpsr[4:0]==5'h10),
					.chickbit_wfenop(myactlr[7]),
					.debug_state(debug_state),
					.setend_dis(1'b0),
					//.ccpass(myccpass),
					.chickbit_pldnop(myactlr[5]),
					.exc_preamble(1'b0),		// unused in opcode coverage - preambles aren't covered here
					.exception(1'b0),		// unused in decoders
					.chickbit_dsb_on_isb(myactlr[36]),
					.lsm_regcnt_bit0(opc_lsm_regcnt[0]),
					.lsm_regcnt_bit1(opc_lsm_regcnt[1]),
					.lsm_regcnt_bit2(opc_lsm_regcnt[2]),
					.lsm_regcnt_bit3(opc_lsm_regcnt[3]),
					.lsm_regcnt_bit4(opc_lsm_regcnt[4]),
					.lsm_regcnt_bit5(opc_lsm_regcnt[5]),
					.lsm_uopcnt_1(opc_lsm_uopcnt_1_at),
					.lsm_uopcnt_2(opc_lsm_uopcnt_2_at)
					
					);
				arm_neon_opcode_coverage.new_opcode(.orig_inst(myopcode),
					.cp15bar_en(1'b0),
					.secure(mysecure),
					.hypervisor(mycpsr[4:0]==5'h1a),
					.chickbit_wfinop(myactlr[8]),
					.user(mycpsr[4:0]==5'h10),
					.chickbit_wfenop(myactlr[7]),
					.debug_state(debug_state),
					.setend_dis(1'b0),
					//.ccpass(myccpass),
					.chickbit_pldnop(myactlr[5]),
					.exc_preamble(1'b0),		// unused in opcode coverage - preambles aren't covered here
					.exception(1'b0),		// unused in decoders
					.chickbit_dsb_on_isb(myactlr[36]),
					.lsm_regcnt_bit0(opc_lsm_regcnt[0]),
					.lsm_regcnt_bit1(opc_lsm_regcnt[1]),
					.lsm_regcnt_bit2(opc_lsm_regcnt[2]),
					.lsm_regcnt_bit3(opc_lsm_regcnt[3]),
					.lsm_regcnt_bit4(opc_lsm_regcnt[4]),
					.lsm_regcnt_bit5(opc_lsm_regcnt[5]),
					.lsm_uopcnt_1(opc_lsm_uopcnt_1_neon),
					.lsm_uopcnt_2(opc_lsm_uopcnt_2_neon)
					);
			end else begin
				thumb_opcode_coverage.new_opcode(.hw1(myopcode[15:0]),
					.hw2(myopcode[31:16]),
					.secure(mysecure),
					.hypervisor(mycpsr[4:0]==5'h1a),
					.in_it_block(|{mycpsr[15:10],mycpsr[26:25]}),
					.chickbit_wfinop(myactlr[8]),
					.user(mycpsr[4:0]==5'h10),
					.isize(mysize),
					.chickbit_wfenop(myactlr[7]),
					.setend_dis(1'b0),
					.debug_state(debug_state),
					//.ccpass(myccpass),
					.chickbit_pldnop(myactlr[5]),
					.it_dis(1'b0),
					.jbit(mycpsr[24]),
					.exception(1'b0),		// unused in decoders
					.chickbit_dsb_on_isb(myactlr[36]),
					.lsm_regcnt_bit0(opc_lsm_regcnt[0]),
					.lsm_regcnt_bit1(opc_lsm_regcnt[1]),
					.lsm_regcnt_bit2(opc_lsm_regcnt[2]),
					.lsm_regcnt_bit3(opc_lsm_regcnt[3]),
					.lsm_regcnt_bit4(opc_lsm_regcnt[4]),
					.lsm_regcnt_bit5(opc_lsm_regcnt[5]),
					.lsm_uopcnt_1(opc_lsm_uopcnt_1_at),
					.lsm_uopcnt_2(opc_lsm_uopcnt_2_at)
					);
				thumb_neon_opcode_coverage.new_opcode(.orig_inst(myopcode),		// will be translated to arm format
					.cp15bar_en(1'b0),
					.secure(mysecure),
					.hypervisor(mycpsr[4:0]==5'h1a),
					.in_it_block(|{mycpsr[15:10],mycpsr[26:25]}),
					.chickbit_wfinop(myactlr[8]),
					.user(mycpsr[4:0]==5'h10),
					.chickbit_wfenop(myactlr[7]),
					.setend_dis(1'b0),
					.debug_state(debug_state),
					//.ccpass(myccpass),
					.chickbit_pldnop(myactlr[5]),
					.exc_preamble(1'b0),		// unused in opcode coverage - preambles aren't covered here
					.exception(1'b0),		// unused in decoders
					.chickbit_dsb_on_isb(myactlr[36]),
					.lsm_regcnt_bit0(opc_lsm_regcnt[0]),
					.lsm_regcnt_bit1(opc_lsm_regcnt[1]),
					.lsm_regcnt_bit2(opc_lsm_regcnt[2]),
					.lsm_regcnt_bit3(opc_lsm_regcnt[3]),
					.lsm_regcnt_bit4(opc_lsm_regcnt[4]),
					.lsm_regcnt_bit5(opc_lsm_regcnt[5]),
					.lsm_uopcnt_1(opc_lsm_uopcnt_1_neon),
					.lsm_uopcnt_2(opc_lsm_uopcnt_2_neon)
					);
			end
		end else begin
			a64_opcode_coverage.new_opcode(.orig_inst(myopcode),
				.chickbit_wfinop(myactlr[8]),
				.el_bit1(mycpsr[3]),
				.chickbit_wfenop(myactlr[7]),
				.debug_state(debug_state),
				.big_endian(1'b0),
				.exc_preamble(1'b0),		// unused in opcode coverage - preambles aren't covered here
				.el_bit0(mycpsr[2]),
				.chickbit_dsb_on_isb(myactlr[36]),
				.chickbit_pldnop(1'b0)
				);
		end
		
		
	endfunction		// isscmp_opc_cov_callback_DPI
	`else

	export "DPI-C" function isscmp_opc_cov_callback_DPI;
	function void isscmp_opc_cov_callback_DPI(bit [31:0] myopcode,bit [31:0] mycpsr,bit [31:0] myscr,bit [31:0] mysctlrns,bit [31:0] mysctlrs,bit [31:0] myactlr,bit [31:0] myother);
	endfunction		// isscmp_opc_cov_callback_DPI
	`endif//}

	
	export "DPI-C" function isscmp_end_of_test_callback_DPI;
	function void isscmp_end_of_test_callback_DPI();
		isscmp_detected_end_of_test = 1'b1;
	endfunction		// isscmp_end_of_test_callback_DPI
	
	export "DPI-C" function isscmp_mismatch_callback_DPI;
	
	function void isscmp_mismatch_callback_DPI();
		if (iss_nofail != 1'b1)
			isscmp_mismatch = 1'b1;
	endfunction		// isscmp_mismatch_callback_DPI
	
	import "DPI-C" context function finalize_isscmp();
	
	export "DPI-C" function isscmp_fatal_error_callback_DPI;
	
	function void isscmp_fatal_error_callback_DPI();
		begin
			isscmp_fatal = 1'b1;
			finalize_isscmp();		//Call to delete ISS so it will generate CT Trace
		end
	endfunction		// isscmp_fatal_error_callback_DPI
	
	export "DPI-C" function isscmp_finish_DPI;
	
	function void isscmp_finish_DPI();
		$display("call to isscmp_finish_DPI - ending simulation\n");
		$finish(0);
	endfunction
	
	initial begin
		isscmp_detected_end_of_test = 1'b0;
		isscmp_fatal                = 1'b0;
		isscmp_idle                 = 1'b0;
		isscmp_mismatch             = 1'b0;
		iss_nofail                  = 1'b0;

		`ifndef DSM_MODEL//{
		if ($value$plusargs("iss_nofail=%d",iss_nofail));
		`endif//}

	end
	
	assign iss_mismatch = isscmp_mismatch;
	assign iss_fatal    = isscmp_fatal;
	assign iss_eot      = isscmp_detected_end_of_test;
	
	///////////////////////////////////////////////////////////////////////
	// Magic Constants that are known by both this and the C++ world
	///////////////////////////////////////////////////////////////////////
	
	`define	T_OPC	4'b0001 // Opcode info
	`define	T_STR	4'b0010 // Store Buffer action
	`define	T_AES	4'b0011 // ARM / Extension / Special retired
	`define T_PSR	4'b0100 // PSR retired
	`define T_SPW	4'b0101 // SP write retired
	`define T_LOD	4'b0110 // Load info
	`define T_DEA	4'b0111 // CommQ entry de-allocated
	`define T_ABT	4'b1011 // Impecise DABORT
	
	// NOTE: If you change the amount of data sent down one of the pipes in a
	// single transaction then you must resize the scemi_output_pipe declaration,
	// otherwise Bad Things will happen that are hard to debug.
	
	import "DPI-C" context function void send_packet_DPI(bit [511:0] buff);
	`define AES_SEND(buff) send_packet_DPI(buff)
	`define OPC_SEND(buff) send_packet_DPI(buff)
	`define PSR_SEND(buff) send_packet_DPI(buff)
	`define STR_SEND(buff) send_packet_DPI(buff)
	`define LOD_SEND(buff) send_packet_DPI(buff)
	`define SPW_SEND(buff) send_packet_DPI(buff)
	`define DEA_SEND(buff) send_packet_DPI(buff)
	`define SEND_IMP_DABT(buff) send_packet_DPI(buff)
	
	import "DPI-C" context function void reset_cpu(int cpu_id, int pins_on_reset, int periphbase_39_8);
	
	import "DPI-C" context function void sync_regfiles(int cpu_id, int clusterid,
		bit debug_state,
		bit [2687:0] arm_rf,		// 42  64-bit regs
		bit [4351:0] ext_rf,		// 136 32-bit regs
		bit [9151:0] sys_rf);		// 143 64-bit regs
	//      import "DPI-C" context function void initialize_arm_rf(int cpu_id, bit [1151:0] buff);  // 36 32-bit regs
	//      import "DPI-C" context function void initialize_ext_rf(int cpu_id, bit [2175:0] buff);  // 68 32-bit regs
	//      import "DPI-C" context function void initialize_sys_rf(int cpu_id, bit [3615:0] buff);  // 110 32-bit regs
	
	int   verbosity;
	int   isscmp_disable;
	
	initial begin

		`ifndef DSM_MODEL//{
		if ($test$plusargs("isscmp_disable")) isscmp_disable = 1;
		else isscmp_disable = 0;
		if ($value$plusargs("iss_verbosity=%d",verbosity));
		else verbosity = 0;
		if(verbosity<4)
			verbosity = 0;		// only turn on verilog verbosity if iss_verbosity is >=5
		`endif//}

	end
	
	export "DPI-C" function isscmp_set_verbosity_DPI;
	function void isscmp_set_verbosity_DPI();
		verbosity = 1;
	endfunction		// isscmp_set_verbosity_DPI
	
	
	///////////////////////////////////////////////////////////////////////
	// copy all architectural state at reset 2 cycles after reset is deasserted
	///////////////////////////////////////////////////////////////////////
	wire [4351:0] ext_rf_full;
	// assign ext_rf_full =
	// 	{
	// 	ext_rf_data00_b0_q,
	// 	ext_rf_data00_b1_q,
	// 	ext_rf_data00_b2_q,
	// 	ext_rf_data00_b3_q,
	// 	ext_rf_data01_b0_q,
	// 	ext_rf_data01_b1_q,
	// 	ext_rf_data01_b2_q,
	// 	ext_rf_data01_b3_q,
	// 	ext_rf_data02_b0_q,
	// 	ext_rf_data02_b1_q,
	// 	ext_rf_data02_b2_q,
	// 	ext_rf_data02_b3_q,
	// 	ext_rf_data03_b0_q,
	// 	ext_rf_data03_b1_q,
	// 	ext_rf_data03_b2_q,
	// 	ext_rf_data03_b3_q,
	// 	ext_rf_data04_b0_q,
	// 	ext_rf_data04_b1_q,
	// 	ext_rf_data04_b2_q,
	// 	ext_rf_data04_b3_q,
	// 	ext_rf_data05_b0_q,
	// 	ext_rf_data05_b1_q,
	// 	ext_rf_data05_b2_q,
	// 	ext_rf_data05_b3_q,
	// 	ext_rf_data06_b0_q,
	// 	ext_rf_data06_b1_q,
	// 	ext_rf_data06_b2_q,
	// 	ext_rf_data06_b3_q,
	// 	ext_rf_data07_b0_q,
	// 	ext_rf_data07_b1_q,
	// 	ext_rf_data07_b2_q,
	// 	ext_rf_data07_b3_q,
	// 	ext_rf_data08_b0_q,
	// 	ext_rf_data08_b1_q,
	// 	ext_rf_data08_b2_q,
	// 	ext_rf_data08_b3_q,
	// 	ext_rf_data09_b0_q,
	// 	ext_rf_data09_b1_q,
	// 	ext_rf_data09_b2_q,
	// 	ext_rf_data09_b3_q,
	// 	ext_rf_data10_b0_q,
	// 	ext_rf_data10_b1_q,
	// 	ext_rf_data10_b2_q,
	// 	ext_rf_data10_b3_q,
	// 	ext_rf_data11_b0_q,
	// 	ext_rf_data11_b1_q,
	// 	ext_rf_data11_b2_q,
	// 	ext_rf_data11_b3_q,
	// 	ext_rf_data12_b0_q,
	// 	ext_rf_data12_b1_q,
	// 	ext_rf_data12_b2_q,
	// 	ext_rf_data12_b3_q,
	// 	ext_rf_data13_b0_q,
	// 	ext_rf_data13_b1_q,
	// 	ext_rf_data13_b2_q,
	// 	ext_rf_data13_b3_q,
	// 	ext_rf_data14_b0_q,
	// 	ext_rf_data14_b1_q,
	// 	ext_rf_data14_b2_q,
	// 	ext_rf_data14_b3_q,
	// 	ext_rf_data15_b0_q,
	// 	ext_rf_data15_b1_q,
	// 	ext_rf_data15_b2_q,
	// 	ext_rf_data15_b3_q,
	// 	ext_rf_data16_b0_q,
	// 	ext_rf_data16_b1_q,
	// 	ext_rf_data16_b2_q,
	// 	ext_rf_data16_b3_q,
	// 	ext_rf_data17_b0_q,
	// 	ext_rf_data17_b1_q,
	// 	ext_rf_data17_b2_q,
	// 	ext_rf_data17_b3_q,
	// 	ext_rf_data18_b0_q,
	// 	ext_rf_data18_b1_q,
	// 	ext_rf_data18_b2_q,
	// 	ext_rf_data18_b3_q,
	// 	ext_rf_data19_b0_q,
	// 	ext_rf_data19_b1_q,
	// 	ext_rf_data19_b2_q,
	// 	ext_rf_data19_b3_q,
	// 	ext_rf_data20_b0_q,
	// 	ext_rf_data20_b1_q,
	// 	ext_rf_data20_b2_q,
	// 	ext_rf_data20_b3_q,
	// 	ext_rf_data21_b0_q,
	// 	ext_rf_data21_b1_q,
	// 	ext_rf_data21_b2_q,
	// 	ext_rf_data21_b3_q,
	// 	ext_rf_data22_b0_q,
	// 	ext_rf_data22_b1_q,
	// 	ext_rf_data22_b2_q,
	// 	ext_rf_data22_b3_q,
	// 	ext_rf_data23_b0_q,
	// 	ext_rf_data23_b1_q,
	// 	ext_rf_data23_b2_q,
	// 	ext_rf_data23_b3_q,
	// 	ext_rf_data24_b0_q,
	// 	ext_rf_data24_b1_q,
	// 	ext_rf_data24_b2_q,
	// 	ext_rf_data24_b3_q,
	// 	ext_rf_data25_b0_q,
	// 	ext_rf_data25_b1_q,
	// 	ext_rf_data25_b2_q,
	// 	ext_rf_data25_b3_q,
	// 	ext_rf_data26_b0_q,
	// 	ext_rf_data26_b1_q,
	// 	ext_rf_data26_b2_q,
	// 	ext_rf_data26_b3_q,
	// 	ext_rf_data27_b0_q,
	// 	ext_rf_data27_b1_q,
	// 	ext_rf_data27_b2_q,
	// 	ext_rf_data27_b3_q,
	// 	ext_rf_data28_b0_q,
	// 	ext_rf_data28_b1_q,
	// 	ext_rf_data28_b2_q,
	// 	ext_rf_data28_b3_q,
	// 	ext_rf_data29_b0_q,
	// 	ext_rf_data29_b1_q,
	// 	ext_rf_data29_b2_q,
	// 	ext_rf_data29_b3_q,
	// 	ext_rf_data30_b0_q,
	// 	ext_rf_data30_b1_q,
	// 	ext_rf_data30_b2_q,
	// 	ext_rf_data30_b3_q,
	// 	ext_rf_data31_b0_q,
	// 	ext_rf_data31_b1_q,
	// 	ext_rf_data31_b2_q,
	// 	ext_rf_data31_b3_q,
	// 	ext_rf_data32_b0_q,
	// 	ext_rf_data32_b1_q,
	// 	ext_rf_data32_b2_q,
	// 	ext_rf_data32_b3_q,
	// 	ext_rf_data33_b0_q,
	// 	ext_rf_data33_b1_q,
	// 	ext_rf_data33_b2_q,
	// 	ext_rf_data33_b3_q
	// 	};
	
	
	// task            call_dpi_sync_regfiles();
	// sync_regfiles(cpuid,
	// 	clusterid,
	// 	debug_state,
	// 	{arm_rf_data00b0_q,
	// 	arm_rf_data00b1_q,
	// 	arm_rf_data01b0_q,
	// 	arm_rf_data01b1_q,
	// 	arm_rf_data02b0_q,
	// 	arm_rf_data02b1_q,
	// 	arm_rf_data03b0_q,
	// 	arm_rf_data03b1_q,
	// 	arm_rf_data04b0_q,
	// 	arm_rf_data04b1_q,
	// 	arm_rf_data05b0_q,
	// 	arm_rf_data05b1_q,
	// 	arm_rf_data06b0_q,
	// 	arm_rf_data06b1_q,
	// 	arm_rf_data07b0_q,
	// 	arm_rf_data07b1_q,
	// 	arm_rf_data08b0_q,
	// 	arm_rf_data08b1_q,
	// 	arm_rf_data09b0_q,
	// 	arm_rf_data09b1_q,
	// 	arm_rf_data10b0_q,
	// 	arm_rf_data10b1_q,
	// 	arm_rf_data11b0_q,
	// 	arm_rf_data11b1_q,
	// 	arm_rf_data12b0_q,
	// 	arm_rf_data12b1_q,
	// 	arm_rf_data13b0_q,
	// 	arm_rf_data13b1_q,
	// 	arm_rf_data14b0_q,
	// 	arm_rf_data14b1_q,
	// 	arm_rf_data15b0_q,
	// 	arm_rf_data15b1_q,
	// 	arm_rf_data16b0_q,
	// 	arm_rf_data16b1_q,
	// 	arm_rf_data17b0_q,
	// 	arm_rf_data17b1_q,
	// 	arm_rf_data18b0_q,
	// 	arm_rf_data18b1_q,
	// 	arm_rf_data19b0_q,
	// 	arm_rf_data19b1_q,
	// 	arm_rf_data20b0_q,
	// 	arm_rf_data20b1_q,
	// 	arm_rf_data21b0_q,
	// 	arm_rf_data21b1_q,
	// 	arm_rf_data22b0_q,
	// 	arm_rf_data22b1_q,
	// 	arm_rf_data23b0_q,
	// 	arm_rf_data23b1_q,
	// 	arm_rf_data24b0_q,
	// 	arm_rf_data24b1_q,
	// 	arm_rf_data25b0_q,
	// 	arm_rf_data25b1_q,
	// 	arm_rf_data26b0_q,
	// 	arm_rf_data26b1_q,
	// 	arm_rf_data27b0_q,
	// 	arm_rf_data27b1_q,
	// 	arm_rf_data28b0_q,
	// 	arm_rf_data28b1_q,
	// 	arm_rf_data29b0_q,
	// 	arm_rf_data29b1_q,
	// 	arm_rf_data30b0_q,
	// 	arm_rf_data30b1_q,
	// 	arm_rf_data31b0_q,
	// 	arm_rf_data31b1_q,
	// 	arm_rf_data32b0_q,
	// 	arm_rf_data32b1_q,
	// 	arm_rf_data33b0_q,
	// 	arm_rf_data33b1_q,
	// 	arm_rf_data34b0_q,
	// 	arm_rf_data34b1_q,
	// 	arm_rf_data35b0_q,
	// 	arm_rf_data35b1_q,
	// 	arm_rf_data36b0_q,
	// 	arm_rf_data36b1_q,
	// 	arm_rf_data37b0_q,
	// 	arm_rf_data37b1_q,
	// 	arm_rf_data38b0_q,
	// 	arm_rf_data38b1_q,
	// 	arm_rf_data39b0_q,
	// 	arm_rf_data39b1_q,
	// 	arm_rf_data40b0_q,
	// 	arm_rf_data40b1_q,
	// 	arm_rf_data41b0_q,
	// 	arm_rf_data41b1_q
	// 	},
	// 	ext_rf_full,
	// 	{{32'h0,cpsr},
	// 	{32'h0,spsr_el1},		//spsr_svc
	// 	{32'h0,spsr_el2},		//spsr_hyp
	// 	{32'h0,spsr_el3},		//spsr_mon
	// 	{32'h0,spsr_abt},
	// 	{32'h0,spsr_und},
	// 	{32'h0,spsr_irq},
	// 	{32'h0,spsr_fiq},
	// 	{32'h0,dspsr},
	// 	{32'h0,fpscr},
	// 	{32'h0,fpexc},
	// 	{32'h0,mvfr0},
	// 	{32'h0,mvfr1},
	// 	{32'h0,mvfr2},
	// 	{32'h0,dec_aa64pfr0_el1},
	// 	{32'h0,dec_aa64pfr1_el1},
	// 	{32'h0,dec_aa64dfr0_el1},
	// 	{32'h0,dec_aa64dfr1_el1},
	// 	{32'h0,dec_aa64afr0_el1},
	// 	{32'h0,dec_aa64afr1_el1},
	// 	{32'h0,dec_aa64isar0_el1},
	// 	{32'h0,dec_aa64isar1_el1},
	// 	{32'h0,dec_aa64mmfr0_el1},
	// 	{32'h0,dec_aa64mmfr1_el1},
	// 	{32'h0,fpsid},
	// 	{32'h0,midr},
	// 	{32'h0,ctr},
	// 	{32'h0,tcmtr},
	// 	{32'h0,tlbtr},
	// 	{32'h0,mpidr},
	// 	{32'h0,dec_pfr0},
	// 	{32'h0,dec_pfr1},
	// 	{32'h0,dec_dfr0},
	// 	{32'h0,dec_afr0},
	// 	{32'h0,dec_mmfr0},
	// 	{32'h0,dec_mmfr1},
	// 	{32'h0,dec_mmfr2},
	// 	{32'h0,dec_mmfr3},
	// 	{32'h0,dec_isar0},
	// 	{32'h0,dec_isar1},
	// 	{32'h0,dec_isar2},
	// 	{32'h0,dec_isar3},
	// 	{32'h0,dec_isar4},
	// 	{32'h0,dec_isar5},
	// 	{32'h0,ccsidr},
	// 	{32'h0,clidr},
	// 	{32'h0,aidr},
	// 	{32'h0,csselr_ns},
	// 	{32'h0,csselr_s},
	// 	{32'h0,vpidr},
	// 	{32'h0,vmpidr},
	// 	{32'h0,sctlr_ns},
	// 	{32'h0,sctlr_s},
	// 	{32'h0,actlr_ns},
	// 	{32'h0,actlr_s},
	// 	{32'h0,cpacr},
	// 	{32'h0,scr},
	// 	{32'h0,sder},
	// 	{32'h0,nsacr},
	// 	{32'h0,hsctlr},
	// 	{32'h0,hactlr},
	// 	{hcr2,hcr},		//Extended Type hcr_el2[63:0] = {hcr2[31:0],hcr[31:0]}: Note that HCR2/HCR are both accessible in AArch32 so sync both to ISSCMP
	// 	{32'h0,hdcr},
	// 	{32'h0,hcptr},
	// 	{32'h0,hstr},
	// 	{32'h0,hacr},
	// 	{32'h0,ttbr0_lo_ns},
	// 	{32'h0,ttbr0_hi_ns},
	// 	{32'h0,ttbr0_lo_s},
	// 	{32'h0,ttbr0_hi_s},
	// 	{32'h0,ttbr1_lo_ns},
	// 	{32'h0,ttbr1_hi_ns},
	// 	{32'h0,ttbr1_lo_s},
	// 	{32'h0,ttbr1_hi_s},
	// 	dsu_aarch64_state ? {tcr_el1} : {32'h0,ttbcr_ns},		//Extended Type: tcr_el1[63:0] = {tcr_el1[63:32],ttbcr_ns[31:0]}
	// 	{tcr_el3},
	// 	{tcr_el2},
	// 	{vtcr_el2},
	// 	{32'h0,dacr_ns},
	// 	{32'h0,dacr_s},
	// 	{32'h0,dfsr_ns},
	// 	{32'h0,dfsr_s},
	// 	{32'h0,ifsr_ns},
	// 	{32'h0,ifsr_s},
	// 	{32'h0,adfsr_ns},
	// 	{32'h0,adfsr_s},
	// 	{32'h0,aifsr_ns},
	// 	{32'h0,aifsr_s},
	// 	{32'h0,hadfsr},
	// 	{32'h0,haifsr},
	// 	{32'h0,hsr},
	// 	{32'h0,dfar_ns},
	// 	{32'h0,ifar_ns},
	// 	//NOTE: dfar_s and ifar_s are only visible in AArch32
	// 	{32'h0,dfar_s},
	// 	{32'h0,ifar_s},
	// 	//NOTE: far_el3 is only available in AArch64
	// 	{far_el3},
	// 	{32'h0,hdfar},
	// 	{32'h0,hifar},
	// 	dsu_aarch64_state ? {hpfar_el2} : {32'h0,hpfar},		//Extended Type: hpfar_el2[63:0] = {hpfar_el2[63:32],hpfar[31:0]}
	// 	{32'h0,prrr_mair0_ns},
	// 	{32'h0,nmrr_mair1_ns},
	// 	{32'h0,prrr_mair0_s},
	// 	{32'h0,nmrr_mair1_s},
	// 	{32'h0,amair0_s},
	// 	{32'h0,amair1_s},
	// 	{32'h0,amair0_ns},
	// 	{32'h0,amair1_ns},
	// 	{32'h0,hmair0},
	// 	{32'h0,hmair1},
	// 	{32'h0,hamair0},
	// 	{32'h0,hamair1},
	// 	dsu_aarch64_state ? {vbar_el1} : {32'h0,vbar_ns},		//Extended Type: vbar_el1[63:0] = {vbar_el1[63:32],vbar_ns[31:0]}
	// 	dsu_aarch64_state ? {vbar_el3} : {32'h0,vbar_s},		//Extended Type: vbar_el3[63:0] = {vbar_el3[63:32],vbar_s[31:0]}
	// 	{32'h0,mvbar},
	// 	{32'h0,isr},
	// 	dsu_aarch64_state ? {vbar_el2} : {32'h0,hvbar},		//Extended Type: vbar_el2[63:0] = {vbar_el2[63:32],hvbar[31:0]}
	// 	{32'h0,fcseidr},
	// 	{32'h0,contextidr_ns},
	// 	{32'h0,contextidr_s},
	// 	dsu_aarch64_state ? {tpidr_el0} : {32'h0,tpidrurw_ns},		//Extended Type: tpidr_el0[63:0] = {tpidr_el0[63:32],tpidrurw_ns[31:0]}
	// 	{32'h0,tpidrurw_s},
	// 	dsu_aarch64_state ? {tpidrro_el0} : {32'h0,tpidruro_ns},		//Extended Type: tpidrro_el0[63:0] = {tpidr_el0[63:32],tpidruro_ns[31:0]}
	// 	{32'h0,tpidruro_s},
	// 	dsu_aarch64_state ? {tpidr_el1} : {32'h0,tpidrprw_ns},		//Extended Type: tpidr_el1[63:0] = {tpidr_el1[63:32],tpidrprw_ns[31:0]}
	// 	dsu_aarch64_state ? {tpidr_el3} : {32'h0,tpidrprw_s},		//Extended Type: tpidr_el3[63:0] = {tpidr_el3[63:32],tpidrprw_s[31:0]}
	// 	dsu_aarch64_state ? {tpidr_el2} : {32'h0,htpidr},		//Extended Type: tpidr_el2[63:0] = {tpidr_el2[63:32],htpidr[31:0]}
	// 	{32'h0,vttbr_lo},
	// 	{32'h0,vttbr_hi},
	// 	{32'h0,httbr_lo},
	// 	{32'h0,httbr_hi},
	// 	{32'h0,teecr},
	// 	{32'h0,jidr},
	// 	{32'h0,teehbr},
	// 	{32'h0,joscr},
	// 	{32'h0,jmcr},
	// 	{32'h0,cptr_el3},
	// 	{32'h0,cpuactlr_el1},
	// 	{32'h0,mdcr_el3},		//sdcr
	// 	{rvbar_el3},
	// 	{rmr_el3}
	// 	//FIXME: Add remotes here as well? If we move to only compare what is changed by the excuted instruction, there is no need for SyncReg call.
	// 	});
	// endtask
		
		// state bit for power cycle
		reg power_cycle_seen;
	initial begin
		power_cycle_seen = 1'b0;
	end
	
	
	
	// detect DS idle for too many cycles (hung)
	// in the top level testbench isscmp_fatal is set and detected by the top level
	// environment to halt simulation in the normal way.  In other testbenches
	// a $finish is used to halt simulation
	`define DS_IDLE_TIMEOUT 32'h00010000
	reg ds_idle_count_enable;
	reg [31:0] ds_idle_count;
	wire [31:0] ds_idle_timeout;
	reg [31:0] ds_idle_timeout_init;
	reg        ds_debug_start_u2;
	reg	dsu_flush_u1;
	reg       ds_flush_u2;
	reg [6:0]	ds_flush_gid_u1;
	reg [6:0]	ds_flush_gid_u2;
	reg [5:0]	ds_flush_type_u1;
	reg	bru_flush_u1;
	reg	bx_flush_u2;
	reg [6:0]	bru_flush_gid_u1;
	reg [6:0]	bx_flush_gid_u2;
	
	reg     flush_u1;
	reg     flush_u2;
	reg     flush_u3;
	reg     flush_u4;
	reg     flush_u5;
	reg     flush_u6;
	reg [6:0]	flush_gid_u1;
	reg [6:0]	flush_gid_u2;
	reg [6:0]	flush_gid_u3;
	reg [6:0]	flush_gid_u4;
	reg [6:0]	flush_gid_u5;
	reg [6:0]	flush_gid_u6;
	
	reg        ds_flush_trgt_aarch64_u1;
	reg        ds_flush_trgt_aarch64_u2;
	reg [5:0]  ds_flush_type_u2;
	wire       stg2_exc_x1;
	reg        stg2_exc_u2;
	reg        stg2_exc_u1;
	reg        stg2_exc_u0;
	assign     stg2_exc_x1 = prc_pabort_stg2_x1_q | prc_dabort_stg2_x1_q;
	
	wire       algn_exc_x1;
	reg        algn_exc_u2;
	reg        algn_exc_u1;
	reg        algn_exc_u0;
	assign     algn_exc_x1 = prc_dabort_algn_x1_q;
	
	wire       sp_algn_exc_x1;
	reg        sp_algn_exc_u2;
	reg        sp_algn_exc_u1;
	reg        sp_algn_exc_u0;
	assign     sp_algn_exc_x1 = prc_dabort_sp_x1_q;
	

	`ifdef DSM_MODEL//{
	
	// DSM does not support +args
	assign  ds_idle_timeout=`DS_IDLE_TIMEOUT;
	
	`else

	// initial blocks are not synthesizable, so are thrown out when building for the emulator.
	// in this case the idle timeout is set to the `define instead possibly being set with a plusarg.
	initial begin
		ds_idle_count_enable = 1'b1;
		ds_idle_count = 0;
		if($value$plusargs("ds_idle_timeout=%d",ds_idle_timeout_init));
		else ds_idle_timeout_init = `DS_IDLE_TIMEOUT;
	end
	

	`ifdef EMULATOR//{
	assign  ds_idle_timeout=`DS_IDLE_TIMEOUT;
	`else

	assign  ds_idle_timeout=ds_idle_timeout_init;
	`endif//}

	`endif//}  // ifdef DSM_MODEL

	
	always @(posedge ck_gclkcr) begin
		if(debug_state || mbist_state) begin
			ds_idle_count_enable = 0;
			ds_idle_count = 0;
		end
		if(dsu_commit_0c1) begin
			ds_idle_count_enable = 1'b1;
			ds_idle_count = 0;
		end
		else if(ds_flush_u2 && (ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_WFI ||
			ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_WFE)) begin
				ds_idle_count_enable = 1'b0;
			ds_idle_count_enable = 0;
		end
		else begin
			if(ds_idle_count_enable && ds_idle_count>=ds_idle_timeout) begin
				if(isscmp_disable == 0) isscmp_fatal = 1'b1;
				$display("%t: FATAL ERROR : CPU%d ds IDLE for more than 0x%08x cycles, must be hung!!!\n",
					$time(),cpuid, ds_idle_timeout);
				$display("To increase the idle timeout, add +ds_idle_timeout=n to your simulator command line");

				`ifdef TOPLEVEL_TESTBENCH //{
				`else

				#1000 $finish;
				`endif//}

			end
			ds_idle_count = ds_idle_count + 1;
		end
	end
	
	///////////////////////////////////////////////////////////////////////
	// sp_sync_done after ds_exception_flush
	///////////////////////////////////////////////////////////////////////
	//
	// pipe sp_sync_done from i1 down to e6 (when all pulls are complete)
	// When a ds_exception_flush occurs, set some state to wait for that sp_sync_done_e6
	// at that point update all of the architectural state to the C world
	
	wire ds_exception_flush_u2;
	reg sp_sync_done_e1;
	reg sp_sync_done_e2;
	reg sp_sync_done_e3;
	reg sp_sync_done_e4;
	reg sp_sync_done_e5;
	reg sp_sync_done_e6;
	reg sp_sync_done_e7;
	reg sp_sync_done_e8;
	reg sp_sync_done_e9;
	//reg waiting_for_sync_done;
	
	
	always@(posedge ck_gclkcr) begin
		if(reset) begin
			// pipe sp_sync_done out to e6
			sp_sync_done_e1 <= `PRJ_DFF_DELAY 1'b0;
			sp_sync_done_e2 <= `PRJ_DFF_DELAY 1'b0;
			sp_sync_done_e3 <= `PRJ_DFF_DELAY 1'b0;
			sp_sync_done_e4 <= `PRJ_DFF_DELAY 1'b0;
			sp_sync_done_e5 <= `PRJ_DFF_DELAY 1'b0;
			sp_sync_done_e6 <= `PRJ_DFF_DELAY 1'b0;
			sp_sync_done_e7 <= `PRJ_DFF_DELAY 1'b0;
			sp_sync_done_e8 <= `PRJ_DFF_DELAY 1'b0;
			sp_sync_done_e9 <= `PRJ_DFF_DELAY 1'b0;
		end
		else begin
			// pipe sp_sync_done out to e6
			sp_sync_done_e1 <= `PRJ_DFF_DELAY sp_sync_done_i1;
			sp_sync_done_e2 <= `PRJ_DFF_DELAY sp_sync_done_e1;
			sp_sync_done_e3 <= `PRJ_DFF_DELAY sp_sync_done_e2;
			sp_sync_done_e4 <= `PRJ_DFF_DELAY sp_sync_done_e3;
			sp_sync_done_e5 <= `PRJ_DFF_DELAY sp_sync_done_e4;
			sp_sync_done_e6 <= `PRJ_DFF_DELAY sp_sync_done_e5;
			sp_sync_done_e7 <= `PRJ_DFF_DELAY sp_sync_done_e6;
			sp_sync_done_e8 <= `PRJ_DFF_DELAY sp_sync_done_e7;
			sp_sync_done_e9 <= `PRJ_DFF_DELAY sp_sync_done_e8;
		end
		
		// state bit to mark when i've seen a ds_exception_flush
		if(reset) begin
			waiting_for_sync_done <= `PRJ_DFF_DELAY 1'b0;
			switch_mode_32To64 <= 1'b0;		//Clear
		end
		else if(ds_exception_flush_u2) begin
			if(waiting_for_sync_done) begin
				$display("FATAL ERROR - shouldn't see ds_exception_flush_u2==1 if waiting_for_sync_done=1\n");
				if(isscmp_disable == 0) isscmp_fatal = 1'b1;
			end
			if(~dsu_aarch64_state & ds_flush_trgt_aarch64_u2) begin		//Exceptions taken in Arch32 and going to Arch64
				//When entering debug_state, those are not mode-changing exceptions
				//`PRJ_DSU_FLUSH_TYPE_DBG_HALT_REQ
				//`PRJ_DSU_FLUSH_TYPE_DBG_HALT_EXIT
				//`PRJ_DSU_FLUSH_TYPE_WTCHPNT
				//`PRJ_DSU_FLUSH_TYPE_BRKPNT_REGHIT
				//`PRJ_DSU_FLUSH_TYPE_BRKPNT_SNGLSTP
				//`PRJ_DSU_FLUSH_TYPE_HLT_INST
				//`PRJ_DSU_FLUSH_TYPE_RST_CATCH
				//`PRJ_DSU_FLUSH_TYPE_EXC_CATCH
				//`PRJ_DSU_FLUSH_TYPE_SW_ACC_TRAP
				//`PRJ_DSU_FLUSH_TYPE_BRKPNT_VECTRP
				//`PRJ_DSU_FLUSH_TYPE_BRKPNT_INST
				if(!ds_debug_start_u2 && !debug_state) begin
					switch_mode_32To64 <= 1'b1;		//Set
				end
			end
			else begin
				switch_mode_32To64 <= 1'b0;		//Clear
			end
			waiting_for_sync_done <= `PRJ_DFF_DELAY 1'b1;
		end
		else if(sp_sync_done_e9) begin
			if(waiting_for_sync_done) begin
				if(~switch_mode_32To64) call_dpi_sync_regfiles();		//Postpone the SyncReg() call till we see dsu_aarch64_state rising edge
			end
			waiting_for_sync_done <= `PRJ_DFF_DELAY 1'b0;
		end
	end
	
	////---------------------- Revised by sbc@2014-04-17 11:35 BEGIN----------------------

	`ifdef RAVEN_COSIM
	
	import "DPI-C" function longint getEntryPtAddr();
	`define INST_MEM_PTR_SIZE 5
	`define INST_MEM_DEPTH (1<<`INST_MEM_PTR_SIZE)
	`define INST_MEM_WIDTH 512
	`define AES_MEM_PTR_SIZE 5
	`define AES_MEM_DEPTH (1<<`AES_MEM_PTR_SIZE)
	`define AES_MEM_WIDTH 512
	`define RF_PTR_SIZE 2
	`define RF_SIZE (1<<`RF_PTR_SIZE)
	
	reg [`INST_MEM_WIDTH-1:0] inst_mem[`INST_MEM_DEPTH-1:0];
	reg [`INST_MEM_PTR_SIZE-1:0]  inst_mem_ptr;
	reg [`AES_MEM_WIDTH-1:0] aes_mem[`AES_MEM_DEPTH-1:0];
	reg [`AES_MEM_PTR_SIZE-1:0]  aes_mem_ptr;
	reg [2687:0] arm_rf[`RF_SIZE-1:0];
	reg [4351:0] ext_rf[`RF_SIZE-1:0];
	reg [9151:0] sys_rf[`RF_SIZE-1:0];
	reg [`RF_PTR_SIZE-1:0] rf_ptr;
	
	int         all_reg_check_flag;
	reg         raven_cosim_debug;
	
	initial begin
		aes_mem_ptr[`AES_MEM_PTR_SIZE-1:0]={`AES_MEM_PTR_SIZE{1'b0}};
		inst_mem_ptr[`INST_MEM_PTR_SIZE-1:0]={`INST_MEM_PTR_SIZE{1'b0}};
		rf_ptr[`RF_PTR_SIZE-1:0]={`RF_PTR_SIZE{1'b0}};
		if ($value$plusargs("raven_cosim_debug=%d",raven_cosim_debug));
		else raven_cosim_debug= 0;
	end
	`endif //RAVEN_COSIM

	////---------------------- Revised by sbc@2014-04-17 11:35 END------------------------
	
	
	always@(posedge ck_gclkcr) begin
		if(dsu_aarch64_state && switch_mode_32To64) begin
			call_dpi_sync_regfiles();		//Send in SyncReg() to update SYSRegisters to A64 values
			switch_mode_32To64 <= 1'b0;
		end
	end
	
	///////////////////////////////////////////////////////////////////////
	// Pipe aes retire i/f out to t3 stage
	///////////////////////////////////////////////////////////////////////

	`ifdef MAIA
	reg resq_wrenx_0p2;
	reg resq_wrenx_1p2;
	reg resq_wrenx_2p2;
	reg resq_wreny_0p2;
	reg resq_wreny_1p2;
	reg resq_wreny_2p2;
	reg [`XM_AES_RTAG_INDEX-1:0] dstx_rtag_0p2_q;
	reg [`XM_AES_RTAG_INDEX-1:0] dstx_rtag_1p2_q;
	reg [`XM_AES_RTAG_INDEX-1:0] dstx_rtag_2p2_q;
	reg [`XM_AES_RTAG_INDEX-1:0] dsty_rtag_0p2_q;
	reg [`XM_AES_RTAG_INDEX-1:0] dsty_rtag_1p2_q;
	reg [`XM_AES_RTAG_INDEX-1:0] dsty_rtag_2p2_q;
	reg [7:0] dstx_atag_0p2_q;
	reg [7:0] dstx_atag_1p2_q;
	reg [7:0] dstx_atag_2p2_q;
	reg [7:0] dsty_atag_0p2_q;
	reg [7:0] dsty_atag_1p2_q;
	reg [7:0] dsty_atag_2p2_q;
	reg dstx_dw_0p2_q;
	reg dstx_dw_1p2_q;
	reg dstx_dw_2p2_q;
	reg dsty_dw_0p2_q;
	reg dsty_dw_1p2_q;
	reg dsty_dw_2p2_q;
	reg [2:0] dstx_type_0p2_q;
	reg [2:0] dstx_type_1p2_q;
	reg [2:0] dstx_type_2p2_q;
	reg [2:0] dsty_type_0p2_q;
	reg [2:0] dsty_type_1p2_q;
	reg [2:0] dsty_type_2p2_q;
	`endif

	
	reg		dsu_aes_retire_vld_0t1;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_0t1;
	
	reg		ds_aes_retire_vld_0t2;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_0t2;
	reg [7:0]	ds_aes_retire_atag_0t2;
	reg [2:0]	ds_aes_retire_type_0t2;
	reg [3:0]	ds_aes_retire_zbits_0t2;
	reg		ds_aes_retire_dw_0t2;
	
	reg		ds_aes_retire_vld_0t3;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_0t3;
	reg [7:0]	ds_aes_retire_atag_0t3;
	reg [2:0]	ds_aes_retire_type_0t3;
	reg [3:0]	ds_aes_retire_zbits_0t3;
	reg		ds_aes_retire_dw_0t3;
	
	reg		dsu_aes_retire_vld_1t1;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_1t1;
	
	reg		ds_aes_retire_vld_1t2;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_1t2;
	reg [7:0]	ds_aes_retire_atag_1t2;
	reg [2:0]	ds_aes_retire_type_1t2;
	reg [3:0]	ds_aes_retire_zbits_1t2;
	reg		ds_aes_retire_dw_1t2;
	
	reg		ds_aes_retire_vld_1t3;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_1t3;
	reg [7:0]	ds_aes_retire_atag_1t3;
	reg [2:0]	ds_aes_retire_type_1t3;
	reg [3:0]	ds_aes_retire_zbits_1t3;
	reg		ds_aes_retire_dw_1t3;
	
	reg		dsu_aes_retire_vld_2t1;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_2t1;
	
	reg		ds_aes_retire_vld_2t2;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_2t2;
	reg [7:0]	ds_aes_retire_atag_2t2;
	reg [2:0]	ds_aes_retire_type_2t2;
	reg [3:0]	ds_aes_retire_zbits_2t2;
	reg		ds_aes_retire_dw_2t2;
	
	reg		ds_aes_retire_vld_2t3;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_2t3;
	reg [7:0]	ds_aes_retire_atag_2t3;
	reg [2:0]	ds_aes_retire_type_2t3;
	reg [3:0]	ds_aes_retire_zbits_2t3;
	reg		ds_aes_retire_dw_2t3;
	
	reg		dsu_aes_retire_vld_3t1;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_3t1;
	
	reg		ds_aes_retire_vld_3t2;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_3t2;
	reg [7:0]	ds_aes_retire_atag_3t2;
	reg [2:0]	ds_aes_retire_type_3t2;
	reg [3:0]	ds_aes_retire_zbits_3t2;
	reg		ds_aes_retire_dw_3t2;
	
	reg		ds_aes_retire_vld_3t3;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_3t3;
	reg [7:0]	ds_aes_retire_atag_3t3;
	reg [2:0]	ds_aes_retire_type_3t3;
	reg [3:0]	ds_aes_retire_zbits_3t3;
	reg		ds_aes_retire_dw_3t3;
	
	reg		dsu_aes_retire_vld_4t1;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_4t1;
	
	reg		ds_aes_retire_vld_4t2;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_4t2;
	reg [7:0]	ds_aes_retire_atag_4t2;
	reg [2:0]	ds_aes_retire_type_4t2;
	reg [3:0]	ds_aes_retire_zbits_4t2;
	reg		ds_aes_retire_dw_4t2;
	
	reg		ds_aes_retire_vld_4t3;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_4t3;
	reg [7:0]	ds_aes_retire_atag_4t3;
	reg [2:0]	ds_aes_retire_type_4t3;
	reg [3:0]	ds_aes_retire_zbits_4t3;
	reg		ds_aes_retire_dw_4t3;
	
	reg		dsu_aes_retire_vld_5t1;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_5t1;
	
	reg		ds_aes_retire_vld_5t2;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_5t2;
	reg [7:0]	ds_aes_retire_atag_5t2;
	reg [2:0]	ds_aes_retire_type_5t2;
	reg [3:0]	ds_aes_retire_zbits_5t2;
	reg		ds_aes_retire_dw_5t2;
	
	reg		ds_aes_retire_vld_5t3;
	reg [`XM_AES_RTAG_INDEX-1:0]	ds_aes_retire_rtag_5t3;
	reg [7:0]	ds_aes_retire_atag_5t3;
	reg [2:0]	ds_aes_retire_type_5t3;
	reg [3:0]	ds_aes_retire_zbits_5t3;
	reg		ds_aes_retire_dw_5t3;
	
	reg [31:0] aes_resq_ret_data_0t3_q;
	reg [31:0] aes_resq_ret_data_1t3_q;
	reg [31:0] aes_resq_ret_data_2t3_q;
	reg [31:0] aes_resq_ret_data_3t3_q;
	reg [31:0] aes_resq_ret_data_4t3_q;
	
	
	// always @ (posedge ck_gclkcr)
	// 	begin
	// 		if ( reset )
	// 		begin
	// 			dsu_aes_retire_vld_0t1 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_0t2 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_0t3 <= `PRJ_DFF_DELAY 1'b0;
	// 		dsu_aes_retire_vld_1t1 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_1t2 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_1t3 <= `PRJ_DFF_DELAY 1'b0;
	// 		dsu_aes_retire_vld_2t1 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_2t2 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_2t3 <= `PRJ_DFF_DELAY 1'b0;
	// 		dsu_aes_retire_vld_3t1 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_3t2 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_3t3 <= `PRJ_DFF_DELAY 1'b0;
	// 		dsu_aes_retire_vld_4t1 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_4t2 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_4t3 <= `PRJ_DFF_DELAY 1'b0;
	// 		dsu_aes_retire_vld_5t1 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_5t2 <= `PRJ_DFF_DELAY 1'b0;
	// 		ds_aes_retire_vld_5t3 <= `PRJ_DFF_DELAY 1'b0;
	// 	end
	// 	else
	// 		begin
				

	// 			`ifdef MAIA
	// 			resq_wrenx_0p2 <= `PRJ_DFF_DELAY resq_wrenx_0p1;
	// 		resq_wrenx_1p2 <= `PRJ_DFF_DELAY resq_wrenx_1p1;
	// 		resq_wrenx_2p2 <= `PRJ_DFF_DELAY resq_wrenx_2p1;
	// 		resq_wreny_0p2 <= `PRJ_DFF_DELAY resq_wreny_0p1;
	// 		resq_wreny_1p2 <= `PRJ_DFF_DELAY resq_wreny_1p1;
	// 		resq_wreny_2p2 <= `PRJ_DFF_DELAY resq_wreny_2p1;
	// 		dstx_rtag_0p2_q <= `PRJ_DFF_DELAY dstx_rtag_0p1_q;
	// 		dstx_rtag_1p2_q <= `PRJ_DFF_DELAY dstx_rtag_1p1_q;
	// 		dstx_rtag_2p2_q <= `PRJ_DFF_DELAY dstx_rtag_2p1_q;
	// 		dsty_rtag_0p2_q <= `PRJ_DFF_DELAY dsty_rtag_0p1_q;
	// 		dsty_rtag_1p2_q <= `PRJ_DFF_DELAY dsty_rtag_1p1_q;
	// 		dsty_rtag_2p2_q <= `PRJ_DFF_DELAY dsty_rtag_2p1_q;
	// 		dstx_atag_0p2_q <= `PRJ_DFF_DELAY dstx_atag_0p1_q;
	// 		dstx_atag_1p2_q <= `PRJ_DFF_DELAY dstx_atag_1p1_q;
	// 		dstx_atag_2p2_q <= `PRJ_DFF_DELAY dstx_atag_2p1_q;
	// 		dsty_atag_0p2_q <= `PRJ_DFF_DELAY dsty_atag_0p1_q;
	// 		dsty_atag_1p2_q <= `PRJ_DFF_DELAY dsty_atag_1p1_q;
	// 		dsty_atag_2p2_q <= `PRJ_DFF_DELAY dsty_atag_2p1_q;
	// 		dstx_dw_0p2_q <= `PRJ_DFF_DELAY dstx_dw_0p1_q;
	// 		dstx_dw_1p2_q <= `PRJ_DFF_DELAY dstx_dw_1p1_q;
	// 		dstx_dw_2p2_q <= `PRJ_DFF_DELAY dstx_dw_2p1_q;
	// 		dsty_dw_0p2_q <= `PRJ_DFF_DELAY dsty_dw_0p1_q;
	// 		dsty_dw_1p2_q <= `PRJ_DFF_DELAY dsty_dw_1p1_q;
	// 		dsty_dw_2p2_q <= `PRJ_DFF_DELAY dsty_dw_2p1_q;
	// 		dstx_type_0p2_q <= `PRJ_DFF_DELAY dstx_type_0p1_q;
	// 		dstx_type_1p2_q <= `PRJ_DFF_DELAY dstx_type_1p1_q;
	// 		dstx_type_2p2_q <= `PRJ_DFF_DELAY dstx_type_2p1_q;
	// 		dsty_type_0p2_q <= `PRJ_DFF_DELAY dsty_type_0p1_q;
	// 		dsty_type_1p2_q <= `PRJ_DFF_DELAY dsty_type_1p1_q;
	// 		dsty_type_2p2_q <= `PRJ_DFF_DELAY dsty_type_2p1_q;
	// 			`endif

				
	// 			ds_aes_retire_vld_0t3       <= `PRJ_DFF_DELAY ds_aes_retire_vld_0t2;
	// 		ds_aes_retire_rtag_0t3[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_0t2[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_0t3[7:0] <= `PRJ_DFF_DELAY ds_aes_retire_atag_0t2[7:0];
	// 		ds_aes_retire_type_0t3[2:0] <= `PRJ_DFF_DELAY ds_aes_retire_type_0t2[2:0];
	// 		ds_aes_retire_zbits_0t3[3:0]<= `PRJ_DFF_DELAY ds_aes_retire_zbits_0t2[3:0];
	// 		ds_aes_retire_dw_0t3        <= `PRJ_DFF_DELAY ds_aes_retire_dw_0t2;
			
	// 		ds_aes_retire_vld_0t2       <= `PRJ_DFF_DELAY dsu_aes_retire_vld_0t1;
	// 		ds_aes_retire_rtag_0t2[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_0t1[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_0t2[7:0] <= `PRJ_DFF_DELAY ds_aes_restore_atag_0t1[7:0];
	// 		ds_aes_retire_type_0t2[2:0] <= `PRJ_DFF_DELAY ds_aes_restore_type_0t1[2:0];
	// 		ds_aes_retire_zbits_0t2[3:0]<= `PRJ_DFF_DELAY ds_aes_restore_zbits_0t1[3:0];
	// 		ds_aes_retire_dw_0t2        <= `PRJ_DFF_DELAY ds_aes_restore_dw_0t1;
			
	// 		dsu_aes_retire_vld_0t1       <= `PRJ_DFF_DELAY ds_aes_retire_vld_0t0;
	// 		ds_aes_retire_rtag_0t1[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_restore_rtag_0t0_0u2[`XM_AES_RTAG_INDEX-1:0];
			
	// 		ds_aes_retire_vld_1t3       <= `PRJ_DFF_DELAY ds_aes_retire_vld_1t2;
	// 		ds_aes_retire_rtag_1t3[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_1t2[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_1t3[7:0] <= `PRJ_DFF_DELAY ds_aes_retire_atag_1t2[7:0];
	// 		ds_aes_retire_type_1t3[2:0] <= `PRJ_DFF_DELAY ds_aes_retire_type_1t2[2:0];
	// 		ds_aes_retire_zbits_1t3[3:0]<= `PRJ_DFF_DELAY ds_aes_retire_zbits_1t2[3:0];
	// 		ds_aes_retire_dw_1t3        <= `PRJ_DFF_DELAY ds_aes_retire_dw_1t2;
			
	// 		ds_aes_retire_vld_1t2       <= `PRJ_DFF_DELAY dsu_aes_retire_vld_1t1;
	// 		ds_aes_retire_rtag_1t2[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_1t1[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_1t2[7:0] <= `PRJ_DFF_DELAY ds_aes_restore_atag_1t1[7:0];
	// 		ds_aes_retire_type_1t2[2:0] <= `PRJ_DFF_DELAY ds_aes_restore_type_1t1[2:0];
	// 		ds_aes_retire_zbits_1t2[3:0]<= `PRJ_DFF_DELAY ds_aes_restore_zbits_1t1[3:0];
	// 		ds_aes_retire_dw_1t2        <= `PRJ_DFF_DELAY ds_aes_restore_dw_1t1;
			
	// 		dsu_aes_retire_vld_1t1       <= `PRJ_DFF_DELAY ds_aes_retire_vld_1t0;
	// 		ds_aes_retire_rtag_1t1[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_restore_rtag_1t0_1u2[`XM_AES_RTAG_INDEX-1:0];
			
	// 		ds_aes_retire_vld_2t3       <= `PRJ_DFF_DELAY ds_aes_retire_vld_2t2;
	// 		ds_aes_retire_rtag_2t3[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_2t2[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_2t3[7:0] <= `PRJ_DFF_DELAY ds_aes_retire_atag_2t2[7:0];
	// 		ds_aes_retire_type_2t3[2:0] <= `PRJ_DFF_DELAY ds_aes_retire_type_2t2[2:0];
	// 		ds_aes_retire_zbits_2t3[3:0]<= `PRJ_DFF_DELAY ds_aes_retire_zbits_2t2[3:0];
	// 		ds_aes_retire_dw_2t3        <= `PRJ_DFF_DELAY ds_aes_retire_dw_2t2;
			
	// 		ds_aes_retire_vld_2t2       <= `PRJ_DFF_DELAY dsu_aes_retire_vld_2t1;
	// 		ds_aes_retire_rtag_2t2[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_2t1[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_2t2[7:0] <= `PRJ_DFF_DELAY ds_aes_restore_atag_2t1[7:0];
	// 		ds_aes_retire_type_2t2[2:0] <= `PRJ_DFF_DELAY ds_aes_restore_type_2t1[2:0];
	// 		ds_aes_retire_zbits_2t2[3:0]<= `PRJ_DFF_DELAY ds_aes_restore_zbits_2t1[3:0];
	// 		ds_aes_retire_dw_2t2        <= `PRJ_DFF_DELAY ds_aes_restore_dw_2t1;
			
	// 		dsu_aes_retire_vld_2t1       <= `PRJ_DFF_DELAY ds_aes_retire_vld_2t0;
	// 		ds_aes_retire_rtag_2t1[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_restore_rtag_2t0_2u2[`XM_AES_RTAG_INDEX-1:0];
			
	// 		ds_aes_retire_vld_3t3       <= `PRJ_DFF_DELAY ds_aes_retire_vld_3t2;
	// 		ds_aes_retire_rtag_3t3[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_3t2[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_3t3[7:0] <= `PRJ_DFF_DELAY ds_aes_retire_atag_3t2[7:0];
	// 		ds_aes_retire_type_3t3[2:0] <= `PRJ_DFF_DELAY ds_aes_retire_type_3t2[2:0];
	// 		ds_aes_retire_zbits_3t3[3:0]<= `PRJ_DFF_DELAY ds_aes_retire_zbits_3t2[3:0];
	// 		ds_aes_retire_dw_3t3        <= `PRJ_DFF_DELAY ds_aes_retire_dw_3t2;
			
	// 		ds_aes_retire_vld_3t2       <= `PRJ_DFF_DELAY dsu_aes_retire_vld_3t1;
	// 		ds_aes_retire_rtag_3t2[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_3t1[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_3t2[7:0] <= `PRJ_DFF_DELAY ds_aes_restore_atag_3t1[7:0];
	// 		ds_aes_retire_type_3t2[2:0] <= `PRJ_DFF_DELAY ds_aes_restore_type_3t1[2:0];
	// 		ds_aes_retire_zbits_3t2[3:0]<= `PRJ_DFF_DELAY ds_aes_restore_zbits_3t1[3:0];
	// 		ds_aes_retire_dw_3t2        <= `PRJ_DFF_DELAY ds_aes_restore_dw_3t1;
			
	// 		dsu_aes_retire_vld_3t1       <= `PRJ_DFF_DELAY ds_aes_retire_vld_3t0;
	// 		ds_aes_retire_rtag_3t1[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_restore_rtag_3t0_3u2[`XM_AES_RTAG_INDEX-1:0];
			
	// 		ds_aes_retire_vld_4t3       <= `PRJ_DFF_DELAY ds_aes_retire_vld_4t2;
	// 		ds_aes_retire_rtag_4t3[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_4t2[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_4t3[7:0] <= `PRJ_DFF_DELAY ds_aes_retire_atag_4t2[7:0];
	// 		ds_aes_retire_type_4t3[2:0] <= `PRJ_DFF_DELAY ds_aes_retire_type_4t2[2:0];
	// 		ds_aes_retire_zbits_4t3[3:0]<= `PRJ_DFF_DELAY ds_aes_retire_zbits_4t2[3:0];
	// 		ds_aes_retire_dw_4t3        <= `PRJ_DFF_DELAY ds_aes_retire_dw_4t2;
			
	// 		ds_aes_retire_vld_4t2       <= `PRJ_DFF_DELAY dsu_aes_retire_vld_4t1;
	// 		ds_aes_retire_rtag_4t2[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_4t1[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_4t2[7:0] <= `PRJ_DFF_DELAY ds_aes_restore_atag_4t1[7:0];
	// 		ds_aes_retire_type_4t2[2:0] <= `PRJ_DFF_DELAY ds_aes_restore_type_4t1[2:0];
	// 		ds_aes_retire_zbits_4t2[3:0]<= `PRJ_DFF_DELAY ds_aes_restore_zbits_4t1[3:0];
	// 		ds_aes_retire_dw_4t2        <= `PRJ_DFF_DELAY ds_aes_restore_dw_4t1;
			
	// 		dsu_aes_retire_vld_4t1       <= `PRJ_DFF_DELAY ds_aes_retire_vld_4t0;
	// 		ds_aes_retire_rtag_4t1[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_restore_rtag_4t0_4u2[`XM_AES_RTAG_INDEX-1:0];
			
	// 		ds_aes_retire_vld_5t3       <= `PRJ_DFF_DELAY ds_aes_retire_vld_5t2;
	// 		ds_aes_retire_rtag_5t3[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_5t2[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_5t3[7:0] <= `PRJ_DFF_DELAY ds_aes_retire_atag_5t2[7:0];
	// 		ds_aes_retire_type_5t3[2:0] <= `PRJ_DFF_DELAY ds_aes_retire_type_5t2[2:0];
	// 		ds_aes_retire_zbits_5t3[3:0]<= `PRJ_DFF_DELAY ds_aes_retire_zbits_5t2[3:0];
	// 		ds_aes_retire_dw_5t3        <= `PRJ_DFF_DELAY ds_aes_retire_dw_5t2;
			
	// 		ds_aes_retire_vld_5t2       <= `PRJ_DFF_DELAY dsu_aes_retire_vld_5t1;
	// 		ds_aes_retire_rtag_5t2[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_retire_rtag_5t1[`XM_AES_RTAG_INDEX-1:0];
	// 		ds_aes_retire_atag_5t2[7:0] <= `PRJ_DFF_DELAY ds_aes_restore_atag_5t1[7:0];
	// 		ds_aes_retire_type_5t2[2:0] <= `PRJ_DFF_DELAY ds_aes_restore_type_5t1[2:0];
	// 		ds_aes_retire_zbits_5t2[3:0]<= `PRJ_DFF_DELAY ds_aes_restore_zbits_5t1[3:0];
	// 		ds_aes_retire_dw_5t2        <= `PRJ_DFF_DELAY ds_aes_restore_dw_5t1;
			
	// 		dsu_aes_retire_vld_5t1       <= `PRJ_DFF_DELAY ds_aes_retire_vld_5t0;
	// 		ds_aes_retire_rtag_5t1[`XM_AES_RTAG_INDEX-1:0] <= `PRJ_DFF_DELAY ds_aes_restore_rtag_5t0_5u2[`XM_AES_RTAG_INDEX-1:0];
			
	// 		aes_resq_ret_data_0t3_q[31:0] <= `PRJ_DFF_DELAY  ds_aes_retire_type_0t2[1:0] == 2'b00

	// 			`ifndef MAIA
	// 			? arm_resq_ret_data_0t2_q
	// 			: ext_resq_ret_data_0t2_q;
	// 			`else

	// 			? (ds_aes_retire_rtag_0t2[0] == 1'b0 ? arm_resq_ret_data_0t2_q : arm_resq_ret_data_1t2_q)
	// 			: (ds_aes_retire_rtag_0t2[0] == 1'b0 ? ext_resq_ret_data_0t2_q : ext_resq_ret_data_1t2_q);
	// 			`endif

	// 			aes_resq_ret_data_1t3_q[31:0] <= `PRJ_DFF_DELAY  ds_aes_retire_type_1t2[1:0] == 2'b00

	// 			`ifndef MAIA
	// 			? arm_resq_ret_data_1t2_q
	// 			: ext_resq_ret_data_1t2_q;
	// 			`else

	// 			? (ds_aes_retire_rtag_0t2[0] == 1'b0 ? arm_resq_ret_data_1t2_q : arm_resq_ret_data_0t2_q)
	// 			: (ds_aes_retire_rtag_0t2[0] == 1'b0 ? ext_resq_ret_data_1t2_q : ext_resq_ret_data_0t2_q);
	// 			`endif

	// 			aes_resq_ret_data_2t3_q[31:0] <= `PRJ_DFF_DELAY  ds_aes_retire_type_2t2[1:0] == 2'b00

	// 			`ifndef MAIA
	// 			? arm_resq_ret_data_2t2_q
	// 			: ext_resq_ret_data_2t2_q;
	// 			`else

	// 			? (ds_aes_retire_rtag_0t2[0] == 1'b0 ? arm_resq_ret_data_2t2_q : arm_resq_ret_data_3t2_q)
	// 			: (ds_aes_retire_rtag_0t2[0] == 1'b0 ? ext_resq_ret_data_2t2_q : ext_resq_ret_data_3t2_q);
	// 			`endif

	// 			aes_resq_ret_data_3t3_q[31:0] <= `PRJ_DFF_DELAY  ds_aes_retire_type_3t2[1:0] == 2'b00

	// 			`ifndef MAIA
	// 			? arm_resq_ret_data_3t2_q
	// 			: ext_resq_ret_data_3t2_q;
	// 			`else

	// 			? (ds_aes_retire_rtag_0t2[0] == 1'b0 ? arm_resq_ret_data_3t2_q : arm_resq_ret_data_2t2_q)
	// 			: (ds_aes_retire_rtag_0t2[0] == 1'b0 ? ext_resq_ret_data_3t2_q : ext_resq_ret_data_2t2_q);
	// 			`endif

	// 			aes_resq_ret_data_4t3_q[31:0] <= `PRJ_DFF_DELAY  ds_aes_retire_type_4t2[1:0] == 2'b00

	// 			`ifndef MAIA
	// 			? arm_resq_ret_data_4t2_q
	// 			: ext_resq_ret_data_4t2_q;
	// 			`else

	// 			? (ds_aes_retire_rtag_0t2[0] == 1'b0 ? arm_resq_ret_data_4t2_q : arm_resq_ret_data_5t2_q)
	// 			: (ds_aes_retire_rtag_0t2[0] == 1'b0 ? ext_resq_ret_data_4t2_q : ext_resq_ret_data_5t2_q);
	// 			`endif

	// 		end
	// 	end
		
	// 	///////////////////////////////////////////////////////////////////////
	// 	// Establish correct register file output data to send, if needed
	// 	///////////////////////////////////////////////////////////////////////
		
	// 	wire [63:0]	arm_send_data_full_0;
		
	wire [63:0]	arm_send_data_full_1;
	wire [63:0]	arm_send_data_full_2;
	wire [63:0]	arm_send_data_full_3;
	wire [63:0]	arm_send_data_full_4;
	wire [63:0]	arm_send_data_full_5;
	
	wire [31:0]	arm_send_data_0;
	wire [31:0]	arm_send_data_1;
	wire [31:0]	arm_send_data_2;
	wire [31:0]	arm_send_data_3;
	wire [31:0]	arm_send_data_4;
	wire [31:0]	arm_send_data_5;
	
	wire [127:0]	ext_send_data_q_0;
	wire [31:0]	ext_send_data_0;
	wire [127:0]	ext_send_data_q_1;
	wire [31:0]	ext_send_data_1;
	wire [127:0]	ext_send_data_q_2;
	wire [31:0]	ext_send_data_2;
	wire [127:0]	ext_send_data_q_3;
	wire [31:0]	ext_send_data_3;
	wire [127:0]	ext_send_data_q_4;
	wire [31:0]	ext_send_data_4;
	wire [127:0]	ext_send_data_q_5;
	wire [31:0]	ext_send_data_5;
	
	wire [31:0]	aes_send_data_0;
	wire [31:0]	aes_send_data_1;
	wire [31:0]	aes_send_data_2;
	wire [31:0]	aes_send_data_3;
	wire [31:0]	aes_send_data_4;
	wire [31:0]	aes_send_data_5;
	
	wire            aes_mask_0t3;
	wire            aes_mask_1t3;
	wire            aes_mask_2t3;
	wire            aes_mask_3t3;
	wire            aes_mask_4t3;
	wire            aes_mask_5t3;
	
	assign arm_send_data_full_0[63:0] =
		(ds_aes_retire_atag_0t3[5:0] == 6'd0)  ? {arm_rf_data00b1_q[31:0],arm_rf_data00b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd1)  ? {arm_rf_data01b1_q[31:0],arm_rf_data01b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd2)  ? {arm_rf_data02b1_q[31:0],arm_rf_data02b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd3)  ? {arm_rf_data03b1_q[31:0],arm_rf_data03b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd4)  ? {arm_rf_data04b1_q[31:0],arm_rf_data04b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd5)  ? {arm_rf_data05b1_q[31:0],arm_rf_data05b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd6)  ? {arm_rf_data06b1_q[31:0],arm_rf_data06b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd7)  ? {arm_rf_data07b1_q[31:0],arm_rf_data07b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd8)  ? {arm_rf_data08b1_q[31:0],arm_rf_data08b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd9)  ? {arm_rf_data09b1_q[31:0],arm_rf_data09b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd10) ? {arm_rf_data10b1_q[31:0],arm_rf_data10b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd11) ? {arm_rf_data11b1_q[31:0],arm_rf_data11b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd12) ? {arm_rf_data12b1_q[31:0],arm_rf_data12b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd13) ? {arm_rf_data13b1_q[31:0],arm_rf_data13b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd14) ? {arm_rf_data14b1_q[31:0],arm_rf_data14b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd15) ? {arm_rf_data15b1_q[31:0],arm_rf_data15b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd16) ? {arm_rf_data16b1_q[31:0],arm_rf_data16b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd17) ? {arm_rf_data17b1_q[31:0],arm_rf_data17b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd18) ? {arm_rf_data18b1_q[31:0],arm_rf_data18b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd19) ? {arm_rf_data19b1_q[31:0],arm_rf_data19b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd20) ? {arm_rf_data20b1_q[31:0],arm_rf_data20b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd21) ? {arm_rf_data21b1_q[31:0],arm_rf_data21b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd22) ? {arm_rf_data22b1_q[31:0],arm_rf_data22b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd23) ? {arm_rf_data23b1_q[31:0],arm_rf_data23b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd24) ? {arm_rf_data24b1_q[31:0],arm_rf_data24b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd25) ? {arm_rf_data25b1_q[31:0],arm_rf_data25b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd26) ? {arm_rf_data26b1_q[31:0],arm_rf_data26b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd27) ? {arm_rf_data27b1_q[31:0],arm_rf_data27b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd28) ? {arm_rf_data28b1_q[31:0],arm_rf_data28b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd29) ? {arm_rf_data29b1_q[31:0],arm_rf_data29b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd30) ? {arm_rf_data30b1_q[31:0],arm_rf_data30b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd31) ? {arm_rf_data31b1_q[31:0],arm_rf_data31b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd32) ? {arm_rf_data32b1_q[31:0],arm_rf_data32b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd33) ? {arm_rf_data33b1_q[31:0],arm_rf_data33b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd34) ? {arm_rf_data34b1_q[31:0],arm_rf_data34b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd35) ? {arm_rf_data35b1_q[31:0],arm_rf_data35b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd36) ? {arm_rf_data36b1_q[31:0],arm_rf_data36b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd37) ? {arm_rf_data37b1_q[31:0],arm_rf_data37b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd38) ? {arm_rf_data38b1_q[31:0],arm_rf_data38b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd39) ? {arm_rf_data39b1_q[31:0],arm_rf_data39b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd40) ? {arm_rf_data40b1_q[31:0],arm_rf_data40b0_q[31:0]} :
		{arm_rf_data41b1_q[31:0],arm_rf_data41b0_q[31:0]};
	
	assign arm_send_data_full_1[63:0] =
		(ds_aes_retire_atag_1t3[5:0] == 6'd0)  ? {arm_rf_data00b1_q[31:0],arm_rf_data00b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd1)  ? {arm_rf_data01b1_q[31:0],arm_rf_data01b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd2)  ? {arm_rf_data02b1_q[31:0],arm_rf_data02b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd3)  ? {arm_rf_data03b1_q[31:0],arm_rf_data03b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd4)  ? {arm_rf_data04b1_q[31:0],arm_rf_data04b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd5)  ? {arm_rf_data05b1_q[31:0],arm_rf_data05b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd6)  ? {arm_rf_data06b1_q[31:0],arm_rf_data06b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd7)  ? {arm_rf_data07b1_q[31:0],arm_rf_data07b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd8)  ? {arm_rf_data08b1_q[31:0],arm_rf_data08b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd9)  ? {arm_rf_data09b1_q[31:0],arm_rf_data09b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd10) ? {arm_rf_data10b1_q[31:0],arm_rf_data10b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd11) ? {arm_rf_data11b1_q[31:0],arm_rf_data11b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd12) ? {arm_rf_data12b1_q[31:0],arm_rf_data12b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd13) ? {arm_rf_data13b1_q[31:0],arm_rf_data13b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd14) ? {arm_rf_data14b1_q[31:0],arm_rf_data14b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd15) ? {arm_rf_data15b1_q[31:0],arm_rf_data15b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd16) ? {arm_rf_data16b1_q[31:0],arm_rf_data16b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd17) ? {arm_rf_data17b1_q[31:0],arm_rf_data17b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd18) ? {arm_rf_data18b1_q[31:0],arm_rf_data18b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd19) ? {arm_rf_data19b1_q[31:0],arm_rf_data19b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd20) ? {arm_rf_data20b1_q[31:0],arm_rf_data20b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd21) ? {arm_rf_data21b1_q[31:0],arm_rf_data21b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd22) ? {arm_rf_data22b1_q[31:0],arm_rf_data22b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd23) ? {arm_rf_data23b1_q[31:0],arm_rf_data23b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd24) ? {arm_rf_data24b1_q[31:0],arm_rf_data24b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd25) ? {arm_rf_data25b1_q[31:0],arm_rf_data25b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd26) ? {arm_rf_data26b1_q[31:0],arm_rf_data26b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd27) ? {arm_rf_data27b1_q[31:0],arm_rf_data27b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd28) ? {arm_rf_data28b1_q[31:0],arm_rf_data28b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd29) ? {arm_rf_data29b1_q[31:0],arm_rf_data29b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd30) ? {arm_rf_data30b1_q[31:0],arm_rf_data30b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd31) ? {arm_rf_data31b1_q[31:0],arm_rf_data31b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd32) ? {arm_rf_data32b1_q[31:0],arm_rf_data32b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd33) ? {arm_rf_data33b1_q[31:0],arm_rf_data33b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd34) ? {arm_rf_data34b1_q[31:0],arm_rf_data34b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd35) ? {arm_rf_data35b1_q[31:0],arm_rf_data35b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd36) ? {arm_rf_data36b1_q[31:0],arm_rf_data36b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd37) ? {arm_rf_data37b1_q[31:0],arm_rf_data37b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd38) ? {arm_rf_data38b1_q[31:0],arm_rf_data38b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd39) ? {arm_rf_data39b1_q[31:0],arm_rf_data39b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd40) ? {arm_rf_data40b1_q[31:0],arm_rf_data40b0_q[31:0]} :
		{arm_rf_data41b1_q[31:0],arm_rf_data41b0_q[31:0]};
	
	assign arm_send_data_full_2[63:0] =
		(ds_aes_retire_atag_2t3[5:0] == 6'd0)  ? {arm_rf_data00b1_q[31:0],arm_rf_data00b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd1)  ? {arm_rf_data01b1_q[31:0],arm_rf_data01b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd2)  ? {arm_rf_data02b1_q[31:0],arm_rf_data02b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd3)  ? {arm_rf_data03b1_q[31:0],arm_rf_data03b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd4)  ? {arm_rf_data04b1_q[31:0],arm_rf_data04b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd5)  ? {arm_rf_data05b1_q[31:0],arm_rf_data05b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd6)  ? {arm_rf_data06b1_q[31:0],arm_rf_data06b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd7)  ? {arm_rf_data07b1_q[31:0],arm_rf_data07b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd8)  ? {arm_rf_data08b1_q[31:0],arm_rf_data08b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd9)  ? {arm_rf_data09b1_q[31:0],arm_rf_data09b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd10) ? {arm_rf_data10b1_q[31:0],arm_rf_data10b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd11) ? {arm_rf_data11b1_q[31:0],arm_rf_data11b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd12) ? {arm_rf_data12b1_q[31:0],arm_rf_data12b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd13) ? {arm_rf_data13b1_q[31:0],arm_rf_data13b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd14) ? {arm_rf_data14b1_q[31:0],arm_rf_data14b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd15) ? {arm_rf_data15b1_q[31:0],arm_rf_data15b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd16) ? {arm_rf_data16b1_q[31:0],arm_rf_data16b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd17) ? {arm_rf_data17b1_q[31:0],arm_rf_data17b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd18) ? {arm_rf_data18b1_q[31:0],arm_rf_data18b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd19) ? {arm_rf_data19b1_q[31:0],arm_rf_data19b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd20) ? {arm_rf_data20b1_q[31:0],arm_rf_data20b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd21) ? {arm_rf_data21b1_q[31:0],arm_rf_data21b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd22) ? {arm_rf_data22b1_q[31:0],arm_rf_data22b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd23) ? {arm_rf_data23b1_q[31:0],arm_rf_data23b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd24) ? {arm_rf_data24b1_q[31:0],arm_rf_data24b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd25) ? {arm_rf_data25b1_q[31:0],arm_rf_data25b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd26) ? {arm_rf_data26b1_q[31:0],arm_rf_data26b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd27) ? {arm_rf_data27b1_q[31:0],arm_rf_data27b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd28) ? {arm_rf_data28b1_q[31:0],arm_rf_data28b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd29) ? {arm_rf_data29b1_q[31:0],arm_rf_data29b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd30) ? {arm_rf_data30b1_q[31:0],arm_rf_data30b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd31) ? {arm_rf_data31b1_q[31:0],arm_rf_data31b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd32) ? {arm_rf_data32b1_q[31:0],arm_rf_data32b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd33) ? {arm_rf_data33b1_q[31:0],arm_rf_data33b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd34) ? {arm_rf_data34b1_q[31:0],arm_rf_data34b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd35) ? {arm_rf_data35b1_q[31:0],arm_rf_data35b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd36) ? {arm_rf_data36b1_q[31:0],arm_rf_data36b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd37) ? {arm_rf_data37b1_q[31:0],arm_rf_data37b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd38) ? {arm_rf_data38b1_q[31:0],arm_rf_data38b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd39) ? {arm_rf_data39b1_q[31:0],arm_rf_data39b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd40) ? {arm_rf_data40b1_q[31:0],arm_rf_data40b0_q[31:0]} :
		{arm_rf_data41b1_q[31:0],arm_rf_data41b0_q[31:0]};
	
	assign arm_send_data_full_3[63:0] =
		(ds_aes_retire_atag_3t3[5:0] == 6'd0)  ? {arm_rf_data00b1_q[31:0],arm_rf_data00b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd1)  ? {arm_rf_data01b1_q[31:0],arm_rf_data01b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd2)  ? {arm_rf_data02b1_q[31:0],arm_rf_data02b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd3)  ? {arm_rf_data03b1_q[31:0],arm_rf_data03b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd4)  ? {arm_rf_data04b1_q[31:0],arm_rf_data04b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd5)  ? {arm_rf_data05b1_q[31:0],arm_rf_data05b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd6)  ? {arm_rf_data06b1_q[31:0],arm_rf_data06b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd7)  ? {arm_rf_data07b1_q[31:0],arm_rf_data07b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd8)  ? {arm_rf_data08b1_q[31:0],arm_rf_data08b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd9)  ? {arm_rf_data09b1_q[31:0],arm_rf_data09b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd10) ? {arm_rf_data10b1_q[31:0],arm_rf_data10b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd11) ? {arm_rf_data11b1_q[31:0],arm_rf_data11b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd12) ? {arm_rf_data12b1_q[31:0],arm_rf_data12b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd13) ? {arm_rf_data13b1_q[31:0],arm_rf_data13b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd14) ? {arm_rf_data14b1_q[31:0],arm_rf_data14b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd15) ? {arm_rf_data15b1_q[31:0],arm_rf_data15b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd16) ? {arm_rf_data16b1_q[31:0],arm_rf_data16b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd17) ? {arm_rf_data17b1_q[31:0],arm_rf_data17b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd18) ? {arm_rf_data18b1_q[31:0],arm_rf_data18b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd19) ? {arm_rf_data19b1_q[31:0],arm_rf_data19b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd20) ? {arm_rf_data20b1_q[31:0],arm_rf_data20b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd21) ? {arm_rf_data21b1_q[31:0],arm_rf_data21b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd22) ? {arm_rf_data22b1_q[31:0],arm_rf_data22b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd23) ? {arm_rf_data23b1_q[31:0],arm_rf_data23b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd24) ? {arm_rf_data24b1_q[31:0],arm_rf_data24b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd25) ? {arm_rf_data25b1_q[31:0],arm_rf_data25b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd26) ? {arm_rf_data26b1_q[31:0],arm_rf_data26b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd27) ? {arm_rf_data27b1_q[31:0],arm_rf_data27b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd28) ? {arm_rf_data28b1_q[31:0],arm_rf_data28b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd29) ? {arm_rf_data29b1_q[31:0],arm_rf_data29b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd30) ? {arm_rf_data30b1_q[31:0],arm_rf_data30b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd31) ? {arm_rf_data31b1_q[31:0],arm_rf_data31b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd32) ? {arm_rf_data32b1_q[31:0],arm_rf_data32b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd33) ? {arm_rf_data33b1_q[31:0],arm_rf_data33b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd34) ? {arm_rf_data34b1_q[31:0],arm_rf_data34b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd35) ? {arm_rf_data35b1_q[31:0],arm_rf_data35b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd36) ? {arm_rf_data36b1_q[31:0],arm_rf_data36b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd37) ? {arm_rf_data37b1_q[31:0],arm_rf_data37b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd38) ? {arm_rf_data38b1_q[31:0],arm_rf_data38b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd39) ? {arm_rf_data39b1_q[31:0],arm_rf_data39b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd40) ? {arm_rf_data40b1_q[31:0],arm_rf_data40b0_q[31:0]} :
		{arm_rf_data41b1_q[31:0],arm_rf_data41b0_q[31:0]};
	
	assign arm_send_data_full_4[63:0] =
		(ds_aes_retire_atag_4t3[5:0] == 6'd0)  ? {arm_rf_data00b1_q[31:0],arm_rf_data00b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd1)  ? {arm_rf_data01b1_q[31:0],arm_rf_data01b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd2)  ? {arm_rf_data02b1_q[31:0],arm_rf_data02b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd3)  ? {arm_rf_data03b1_q[31:0],arm_rf_data03b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd4)  ? {arm_rf_data04b1_q[31:0],arm_rf_data04b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd5)  ? {arm_rf_data05b1_q[31:0],arm_rf_data05b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd6)  ? {arm_rf_data06b1_q[31:0],arm_rf_data06b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd7)  ? {arm_rf_data07b1_q[31:0],arm_rf_data07b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd8)  ? {arm_rf_data08b1_q[31:0],arm_rf_data08b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd9)  ? {arm_rf_data09b1_q[31:0],arm_rf_data09b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd10) ? {arm_rf_data10b1_q[31:0],arm_rf_data10b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd11) ? {arm_rf_data11b1_q[31:0],arm_rf_data11b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd12) ? {arm_rf_data12b1_q[31:0],arm_rf_data12b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd13) ? {arm_rf_data13b1_q[31:0],arm_rf_data13b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd14) ? {arm_rf_data14b1_q[31:0],arm_rf_data14b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd15) ? {arm_rf_data15b1_q[31:0],arm_rf_data15b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd16) ? {arm_rf_data16b1_q[31:0],arm_rf_data16b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd17) ? {arm_rf_data17b1_q[31:0],arm_rf_data17b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd18) ? {arm_rf_data18b1_q[31:0],arm_rf_data18b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd19) ? {arm_rf_data19b1_q[31:0],arm_rf_data19b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd20) ? {arm_rf_data20b1_q[31:0],arm_rf_data20b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd21) ? {arm_rf_data21b1_q[31:0],arm_rf_data21b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd22) ? {arm_rf_data22b1_q[31:0],arm_rf_data22b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd23) ? {arm_rf_data23b1_q[31:0],arm_rf_data23b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd24) ? {arm_rf_data24b1_q[31:0],arm_rf_data24b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd25) ? {arm_rf_data25b1_q[31:0],arm_rf_data25b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd26) ? {arm_rf_data26b1_q[31:0],arm_rf_data26b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd27) ? {arm_rf_data27b1_q[31:0],arm_rf_data27b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd28) ? {arm_rf_data28b1_q[31:0],arm_rf_data28b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd29) ? {arm_rf_data29b1_q[31:0],arm_rf_data29b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd30) ? {arm_rf_data30b1_q[31:0],arm_rf_data30b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd31) ? {arm_rf_data31b1_q[31:0],arm_rf_data31b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd32) ? {arm_rf_data32b1_q[31:0],arm_rf_data32b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd33) ? {arm_rf_data33b1_q[31:0],arm_rf_data33b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd34) ? {arm_rf_data34b1_q[31:0],arm_rf_data34b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd35) ? {arm_rf_data35b1_q[31:0],arm_rf_data35b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd36) ? {arm_rf_data36b1_q[31:0],arm_rf_data36b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd37) ? {arm_rf_data37b1_q[31:0],arm_rf_data37b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd38) ? {arm_rf_data38b1_q[31:0],arm_rf_data38b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd39) ? {arm_rf_data39b1_q[31:0],arm_rf_data39b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd40) ? {arm_rf_data40b1_q[31:0],arm_rf_data40b0_q[31:0]} :
		{arm_rf_data41b1_q[31:0],arm_rf_data41b0_q[31:0]};
	
	assign arm_send_data_full_5[63:0] =
		(ds_aes_retire_atag_5t3[5:0] == 6'd0)  ? {arm_rf_data00b1_q[31:0],arm_rf_data00b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd1)  ? {arm_rf_data01b1_q[31:0],arm_rf_data01b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd2)  ? {arm_rf_data02b1_q[31:0],arm_rf_data02b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd3)  ? {arm_rf_data03b1_q[31:0],arm_rf_data03b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd4)  ? {arm_rf_data04b1_q[31:0],arm_rf_data04b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd5)  ? {arm_rf_data05b1_q[31:0],arm_rf_data05b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd6)  ? {arm_rf_data06b1_q[31:0],arm_rf_data06b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd7)  ? {arm_rf_data07b1_q[31:0],arm_rf_data07b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd8)  ? {arm_rf_data08b1_q[31:0],arm_rf_data08b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd9)  ? {arm_rf_data09b1_q[31:0],arm_rf_data09b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd10) ? {arm_rf_data10b1_q[31:0],arm_rf_data10b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd11) ? {arm_rf_data11b1_q[31:0],arm_rf_data11b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd12) ? {arm_rf_data12b1_q[31:0],arm_rf_data12b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd13) ? {arm_rf_data13b1_q[31:0],arm_rf_data13b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd14) ? {arm_rf_data14b1_q[31:0],arm_rf_data14b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd15) ? {arm_rf_data15b1_q[31:0],arm_rf_data15b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd16) ? {arm_rf_data16b1_q[31:0],arm_rf_data16b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd17) ? {arm_rf_data17b1_q[31:0],arm_rf_data17b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd18) ? {arm_rf_data18b1_q[31:0],arm_rf_data18b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd19) ? {arm_rf_data19b1_q[31:0],arm_rf_data19b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd20) ? {arm_rf_data20b1_q[31:0],arm_rf_data20b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd21) ? {arm_rf_data21b1_q[31:0],arm_rf_data21b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd22) ? {arm_rf_data22b1_q[31:0],arm_rf_data22b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd23) ? {arm_rf_data23b1_q[31:0],arm_rf_data23b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd24) ? {arm_rf_data24b1_q[31:0],arm_rf_data24b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd25) ? {arm_rf_data25b1_q[31:0],arm_rf_data25b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd26) ? {arm_rf_data26b1_q[31:0],arm_rf_data26b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd27) ? {arm_rf_data27b1_q[31:0],arm_rf_data27b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd28) ? {arm_rf_data28b1_q[31:0],arm_rf_data28b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd29) ? {arm_rf_data29b1_q[31:0],arm_rf_data29b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd30) ? {arm_rf_data30b1_q[31:0],arm_rf_data30b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd31) ? {arm_rf_data31b1_q[31:0],arm_rf_data31b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd32) ? {arm_rf_data32b1_q[31:0],arm_rf_data32b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd33) ? {arm_rf_data33b1_q[31:0],arm_rf_data33b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd34) ? {arm_rf_data34b1_q[31:0],arm_rf_data34b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd35) ? {arm_rf_data35b1_q[31:0],arm_rf_data35b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd36) ? {arm_rf_data36b1_q[31:0],arm_rf_data36b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd37) ? {arm_rf_data37b1_q[31:0],arm_rf_data37b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd38) ? {arm_rf_data38b1_q[31:0],arm_rf_data38b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd39) ? {arm_rf_data39b1_q[31:0],arm_rf_data39b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd40) ? {arm_rf_data40b1_q[31:0],arm_rf_data40b0_q[31:0]} :
		{arm_rf_data41b1_q[31:0],arm_rf_data41b0_q[31:0]};
	
	assign arm_send_data_0[31:0] = ds_aes_retire_atag_0t3[7:6]==2'b01 ? arm_send_data_full_0[63:32]
		: arm_send_data_full_0[31:00];
	assign arm_send_data_1[31:0] = ds_aes_retire_atag_1t3[7:6]==2'b01 ? arm_send_data_full_1[63:32]
		: arm_send_data_full_1[31:00];
	assign arm_send_data_2[31:0] = ds_aes_retire_atag_2t3[7:6]==2'b01 ? arm_send_data_full_2[63:32]
		: arm_send_data_full_2[31:00];
	assign arm_send_data_3[31:0] = ds_aes_retire_atag_3t3[7:6]==2'b01 ? arm_send_data_full_3[63:32]
		: arm_send_data_full_3[31:00];
	assign arm_send_data_4[31:0] = ds_aes_retire_atag_4t3[7:6]==2'b01 ? arm_send_data_full_4[63:32]
		: arm_send_data_full_4[31:00];
	assign arm_send_data_5[31:0] = ds_aes_retire_atag_5t3[7:6]==2'b01 ? arm_send_data_full_5[63:32]
		: arm_send_data_full_5[31:00];
	
	assign ext_send_data_q_0[127:0] =
		(ds_aes_retire_atag_0t3[5:0] == 6'd0)  ? {ext_rf_data00_b3_q[31:0],ext_rf_data00_b2_q[31:0],ext_rf_data00_b1_q[31:0],ext_rf_data00_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd1)  ? {ext_rf_data01_b3_q[31:0],ext_rf_data01_b2_q[31:0],ext_rf_data01_b1_q[31:0],ext_rf_data01_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd2)  ? {ext_rf_data02_b3_q[31:0],ext_rf_data02_b2_q[31:0],ext_rf_data02_b1_q[31:0],ext_rf_data02_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd3)  ? {ext_rf_data03_b3_q[31:0],ext_rf_data03_b2_q[31:0],ext_rf_data03_b1_q[31:0],ext_rf_data03_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd4)  ? {ext_rf_data04_b3_q[31:0],ext_rf_data04_b2_q[31:0],ext_rf_data04_b1_q[31:0],ext_rf_data04_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd5)  ? {ext_rf_data05_b3_q[31:0],ext_rf_data05_b2_q[31:0],ext_rf_data05_b1_q[31:0],ext_rf_data05_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd6)  ? {ext_rf_data06_b3_q[31:0],ext_rf_data06_b2_q[31:0],ext_rf_data06_b1_q[31:0],ext_rf_data06_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd7)  ? {ext_rf_data07_b3_q[31:0],ext_rf_data07_b2_q[31:0],ext_rf_data07_b1_q[31:0],ext_rf_data07_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd8)  ? {ext_rf_data08_b3_q[31:0],ext_rf_data08_b2_q[31:0],ext_rf_data08_b1_q[31:0],ext_rf_data08_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd9)  ? {ext_rf_data09_b3_q[31:0],ext_rf_data09_b2_q[31:0],ext_rf_data09_b1_q[31:0],ext_rf_data09_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd10) ? {ext_rf_data10_b3_q[31:0],ext_rf_data10_b2_q[31:0],ext_rf_data10_b1_q[31:0],ext_rf_data10_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd11) ? {ext_rf_data11_b3_q[31:0],ext_rf_data11_b2_q[31:0],ext_rf_data11_b1_q[31:0],ext_rf_data11_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd12) ? {ext_rf_data12_b3_q[31:0],ext_rf_data12_b2_q[31:0],ext_rf_data12_b1_q[31:0],ext_rf_data12_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd13) ? {ext_rf_data13_b3_q[31:0],ext_rf_data13_b2_q[31:0],ext_rf_data13_b1_q[31:0],ext_rf_data13_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd14) ? {ext_rf_data14_b3_q[31:0],ext_rf_data14_b2_q[31:0],ext_rf_data14_b1_q[31:0],ext_rf_data14_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd15) ? {ext_rf_data15_b3_q[31:0],ext_rf_data15_b2_q[31:0],ext_rf_data15_b1_q[31:0],ext_rf_data15_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd16) ? {ext_rf_data16_b3_q[31:0],ext_rf_data16_b2_q[31:0],ext_rf_data16_b1_q[31:0],ext_rf_data16_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd17) ? {ext_rf_data17_b3_q[31:0],ext_rf_data17_b2_q[31:0],ext_rf_data17_b1_q[31:0],ext_rf_data17_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd18) ? {ext_rf_data18_b3_q[31:0],ext_rf_data18_b2_q[31:0],ext_rf_data18_b1_q[31:0],ext_rf_data18_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd19) ? {ext_rf_data19_b3_q[31:0],ext_rf_data19_b2_q[31:0],ext_rf_data19_b1_q[31:0],ext_rf_data19_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd20) ? {ext_rf_data20_b3_q[31:0],ext_rf_data20_b2_q[31:0],ext_rf_data20_b1_q[31:0],ext_rf_data20_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd21) ? {ext_rf_data21_b3_q[31:0],ext_rf_data21_b2_q[31:0],ext_rf_data21_b1_q[31:0],ext_rf_data21_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd22) ? {ext_rf_data22_b3_q[31:0],ext_rf_data22_b2_q[31:0],ext_rf_data22_b1_q[31:0],ext_rf_data22_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd23) ? {ext_rf_data23_b3_q[31:0],ext_rf_data23_b2_q[31:0],ext_rf_data23_b1_q[31:0],ext_rf_data23_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd24) ? {ext_rf_data24_b3_q[31:0],ext_rf_data24_b2_q[31:0],ext_rf_data24_b1_q[31:0],ext_rf_data24_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd25) ? {ext_rf_data25_b3_q[31:0],ext_rf_data25_b2_q[31:0],ext_rf_data25_b1_q[31:0],ext_rf_data25_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd26) ? {ext_rf_data26_b3_q[31:0],ext_rf_data26_b2_q[31:0],ext_rf_data26_b1_q[31:0],ext_rf_data26_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd27) ? {ext_rf_data27_b3_q[31:0],ext_rf_data27_b2_q[31:0],ext_rf_data27_b1_q[31:0],ext_rf_data27_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd28) ? {ext_rf_data28_b3_q[31:0],ext_rf_data28_b2_q[31:0],ext_rf_data28_b1_q[31:0],ext_rf_data28_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd29) ? {ext_rf_data29_b3_q[31:0],ext_rf_data29_b2_q[31:0],ext_rf_data29_b1_q[31:0],ext_rf_data29_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd30) ? {ext_rf_data30_b3_q[31:0],ext_rf_data30_b2_q[31:0],ext_rf_data30_b1_q[31:0],ext_rf_data30_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd31) ? {ext_rf_data31_b3_q[31:0],ext_rf_data31_b2_q[31:0],ext_rf_data31_b1_q[31:0],ext_rf_data31_b0_q[31:0]} :
		(ds_aes_retire_atag_0t3[5:0] == 6'd32) ? {ext_rf_data32_b3_q[31:0],ext_rf_data32_b2_q[31:0],ext_rf_data32_b1_q[31:0],ext_rf_data32_b0_q[31:0]} :
		{ext_rf_data33_b3_q[31:0],ext_rf_data33_b2_q[31:0],ext_rf_data33_b1_q[31:0],ext_rf_data33_b0_q[31:0]};
	
	assign ext_send_data_q_1[127:0] =
		(ds_aes_retire_atag_1t3[5:0] == 6'd0)  ? {ext_rf_data00_b3_q[31:0],ext_rf_data00_b2_q[31:0],ext_rf_data00_b1_q[31:0],ext_rf_data00_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd1)  ? {ext_rf_data01_b3_q[31:0],ext_rf_data01_b2_q[31:0],ext_rf_data01_b1_q[31:0],ext_rf_data01_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd2)  ? {ext_rf_data02_b3_q[31:0],ext_rf_data02_b2_q[31:0],ext_rf_data02_b1_q[31:0],ext_rf_data02_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd3)  ? {ext_rf_data03_b3_q[31:0],ext_rf_data03_b2_q[31:0],ext_rf_data03_b1_q[31:0],ext_rf_data03_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd4)  ? {ext_rf_data04_b3_q[31:0],ext_rf_data04_b2_q[31:0],ext_rf_data04_b1_q[31:0],ext_rf_data04_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd5)  ? {ext_rf_data05_b3_q[31:0],ext_rf_data05_b2_q[31:0],ext_rf_data05_b1_q[31:0],ext_rf_data05_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd6)  ? {ext_rf_data06_b3_q[31:0],ext_rf_data06_b2_q[31:0],ext_rf_data06_b1_q[31:0],ext_rf_data06_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd7)  ? {ext_rf_data07_b3_q[31:0],ext_rf_data07_b2_q[31:0],ext_rf_data07_b1_q[31:0],ext_rf_data07_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd8)  ? {ext_rf_data08_b3_q[31:0],ext_rf_data08_b2_q[31:0],ext_rf_data08_b1_q[31:0],ext_rf_data08_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd9)  ? {ext_rf_data09_b3_q[31:0],ext_rf_data09_b2_q[31:0],ext_rf_data09_b1_q[31:0],ext_rf_data09_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd10) ? {ext_rf_data10_b3_q[31:0],ext_rf_data10_b2_q[31:0],ext_rf_data10_b1_q[31:0],ext_rf_data10_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd11) ? {ext_rf_data11_b3_q[31:0],ext_rf_data11_b2_q[31:0],ext_rf_data11_b1_q[31:0],ext_rf_data11_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd12) ? {ext_rf_data12_b3_q[31:0],ext_rf_data12_b2_q[31:0],ext_rf_data12_b1_q[31:0],ext_rf_data12_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd13) ? {ext_rf_data13_b3_q[31:0],ext_rf_data13_b2_q[31:0],ext_rf_data13_b1_q[31:0],ext_rf_data13_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd14) ? {ext_rf_data14_b3_q[31:0],ext_rf_data14_b2_q[31:0],ext_rf_data14_b1_q[31:0],ext_rf_data14_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd15) ? {ext_rf_data15_b3_q[31:0],ext_rf_data15_b2_q[31:0],ext_rf_data15_b1_q[31:0],ext_rf_data15_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd16) ? {ext_rf_data16_b3_q[31:0],ext_rf_data16_b2_q[31:0],ext_rf_data16_b1_q[31:0],ext_rf_data16_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd17) ? {ext_rf_data17_b3_q[31:0],ext_rf_data17_b2_q[31:0],ext_rf_data17_b1_q[31:0],ext_rf_data17_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd18) ? {ext_rf_data18_b3_q[31:0],ext_rf_data18_b2_q[31:0],ext_rf_data18_b1_q[31:0],ext_rf_data18_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd19) ? {ext_rf_data19_b3_q[31:0],ext_rf_data19_b2_q[31:0],ext_rf_data19_b1_q[31:0],ext_rf_data19_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd20) ? {ext_rf_data20_b3_q[31:0],ext_rf_data20_b2_q[31:0],ext_rf_data20_b1_q[31:0],ext_rf_data20_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd21) ? {ext_rf_data21_b3_q[31:0],ext_rf_data21_b2_q[31:0],ext_rf_data21_b1_q[31:0],ext_rf_data21_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd22) ? {ext_rf_data22_b3_q[31:0],ext_rf_data22_b2_q[31:0],ext_rf_data22_b1_q[31:0],ext_rf_data22_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd23) ? {ext_rf_data23_b3_q[31:0],ext_rf_data23_b2_q[31:0],ext_rf_data23_b1_q[31:0],ext_rf_data23_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd24) ? {ext_rf_data24_b3_q[31:0],ext_rf_data24_b2_q[31:0],ext_rf_data24_b1_q[31:0],ext_rf_data24_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd25) ? {ext_rf_data25_b3_q[31:0],ext_rf_data25_b2_q[31:0],ext_rf_data25_b1_q[31:0],ext_rf_data25_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd26) ? {ext_rf_data26_b3_q[31:0],ext_rf_data26_b2_q[31:0],ext_rf_data26_b1_q[31:0],ext_rf_data26_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd27) ? {ext_rf_data27_b3_q[31:0],ext_rf_data27_b2_q[31:0],ext_rf_data27_b1_q[31:0],ext_rf_data27_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd28) ? {ext_rf_data28_b3_q[31:0],ext_rf_data28_b2_q[31:0],ext_rf_data28_b1_q[31:0],ext_rf_data28_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd29) ? {ext_rf_data29_b3_q[31:0],ext_rf_data29_b2_q[31:0],ext_rf_data29_b1_q[31:0],ext_rf_data29_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd30) ? {ext_rf_data30_b3_q[31:0],ext_rf_data30_b2_q[31:0],ext_rf_data30_b1_q[31:0],ext_rf_data30_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd31) ? {ext_rf_data31_b3_q[31:0],ext_rf_data31_b2_q[31:0],ext_rf_data31_b1_q[31:0],ext_rf_data31_b0_q[31:0]} :
		(ds_aes_retire_atag_1t3[5:0] == 6'd32) ? {ext_rf_data32_b3_q[31:0],ext_rf_data32_b2_q[31:0],ext_rf_data32_b1_q[31:0],ext_rf_data32_b0_q[31:0]} :
		{ext_rf_data33_b3_q[31:0],ext_rf_data33_b2_q[31:0],ext_rf_data33_b1_q[31:0],ext_rf_data33_b0_q[31:0]};
	
	assign ext_send_data_q_2[127:0] =
		(ds_aes_retire_atag_2t3[5:0] == 6'd0)  ? {ext_rf_data00_b3_q[31:0],ext_rf_data00_b2_q[31:0],ext_rf_data00_b1_q[31:0],ext_rf_data00_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd1)  ? {ext_rf_data01_b3_q[31:0],ext_rf_data01_b2_q[31:0],ext_rf_data01_b1_q[31:0],ext_rf_data01_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd2)  ? {ext_rf_data02_b3_q[31:0],ext_rf_data02_b2_q[31:0],ext_rf_data02_b1_q[31:0],ext_rf_data02_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd3)  ? {ext_rf_data03_b3_q[31:0],ext_rf_data03_b2_q[31:0],ext_rf_data03_b1_q[31:0],ext_rf_data03_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd4)  ? {ext_rf_data04_b3_q[31:0],ext_rf_data04_b2_q[31:0],ext_rf_data04_b1_q[31:0],ext_rf_data04_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd5)  ? {ext_rf_data05_b3_q[31:0],ext_rf_data05_b2_q[31:0],ext_rf_data05_b1_q[31:0],ext_rf_data05_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd6)  ? {ext_rf_data06_b3_q[31:0],ext_rf_data06_b2_q[31:0],ext_rf_data06_b1_q[31:0],ext_rf_data06_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd7)  ? {ext_rf_data07_b3_q[31:0],ext_rf_data07_b2_q[31:0],ext_rf_data07_b1_q[31:0],ext_rf_data07_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd8)  ? {ext_rf_data08_b3_q[31:0],ext_rf_data08_b2_q[31:0],ext_rf_data08_b1_q[31:0],ext_rf_data08_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd9)  ? {ext_rf_data09_b3_q[31:0],ext_rf_data09_b2_q[31:0],ext_rf_data09_b1_q[31:0],ext_rf_data09_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd10) ? {ext_rf_data10_b3_q[31:0],ext_rf_data10_b2_q[31:0],ext_rf_data10_b1_q[31:0],ext_rf_data10_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd11) ? {ext_rf_data11_b3_q[31:0],ext_rf_data11_b2_q[31:0],ext_rf_data11_b1_q[31:0],ext_rf_data11_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd12) ? {ext_rf_data12_b3_q[31:0],ext_rf_data12_b2_q[31:0],ext_rf_data12_b1_q[31:0],ext_rf_data12_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd13) ? {ext_rf_data13_b3_q[31:0],ext_rf_data13_b2_q[31:0],ext_rf_data13_b1_q[31:0],ext_rf_data13_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd14) ? {ext_rf_data14_b3_q[31:0],ext_rf_data14_b2_q[31:0],ext_rf_data14_b1_q[31:0],ext_rf_data14_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd15) ? {ext_rf_data15_b3_q[31:0],ext_rf_data15_b2_q[31:0],ext_rf_data15_b1_q[31:0],ext_rf_data15_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd16) ? {ext_rf_data16_b3_q[31:0],ext_rf_data16_b2_q[31:0],ext_rf_data16_b1_q[31:0],ext_rf_data16_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd17) ? {ext_rf_data17_b3_q[31:0],ext_rf_data17_b2_q[31:0],ext_rf_data17_b1_q[31:0],ext_rf_data17_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd18) ? {ext_rf_data18_b3_q[31:0],ext_rf_data18_b2_q[31:0],ext_rf_data18_b1_q[31:0],ext_rf_data18_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd19) ? {ext_rf_data19_b3_q[31:0],ext_rf_data19_b2_q[31:0],ext_rf_data19_b1_q[31:0],ext_rf_data19_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd20) ? {ext_rf_data20_b3_q[31:0],ext_rf_data20_b2_q[31:0],ext_rf_data20_b1_q[31:0],ext_rf_data20_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd21) ? {ext_rf_data21_b3_q[31:0],ext_rf_data21_b2_q[31:0],ext_rf_data21_b1_q[31:0],ext_rf_data21_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd22) ? {ext_rf_data22_b3_q[31:0],ext_rf_data22_b2_q[31:0],ext_rf_data22_b1_q[31:0],ext_rf_data22_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd23) ? {ext_rf_data23_b3_q[31:0],ext_rf_data23_b2_q[31:0],ext_rf_data23_b1_q[31:0],ext_rf_data23_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd24) ? {ext_rf_data24_b3_q[31:0],ext_rf_data24_b2_q[31:0],ext_rf_data24_b1_q[31:0],ext_rf_data24_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd25) ? {ext_rf_data25_b3_q[31:0],ext_rf_data25_b2_q[31:0],ext_rf_data25_b1_q[31:0],ext_rf_data25_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd26) ? {ext_rf_data26_b3_q[31:0],ext_rf_data26_b2_q[31:0],ext_rf_data26_b1_q[31:0],ext_rf_data26_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd27) ? {ext_rf_data27_b3_q[31:0],ext_rf_data27_b2_q[31:0],ext_rf_data27_b1_q[31:0],ext_rf_data27_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd28) ? {ext_rf_data28_b3_q[31:0],ext_rf_data28_b2_q[31:0],ext_rf_data28_b1_q[31:0],ext_rf_data28_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd29) ? {ext_rf_data29_b3_q[31:0],ext_rf_data29_b2_q[31:0],ext_rf_data29_b1_q[31:0],ext_rf_data29_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd30) ? {ext_rf_data30_b3_q[31:0],ext_rf_data30_b2_q[31:0],ext_rf_data30_b1_q[31:0],ext_rf_data30_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd31) ? {ext_rf_data31_b3_q[31:0],ext_rf_data31_b2_q[31:0],ext_rf_data31_b1_q[31:0],ext_rf_data31_b0_q[31:0]} :
		(ds_aes_retire_atag_2t3[5:0] == 6'd32) ? {ext_rf_data32_b3_q[31:0],ext_rf_data32_b2_q[31:0],ext_rf_data32_b1_q[31:0],ext_rf_data32_b0_q[31:0]} :
		{ext_rf_data33_b3_q[31:0],ext_rf_data33_b2_q[31:0],ext_rf_data33_b1_q[31:0],ext_rf_data33_b0_q[31:0]};
	
	assign ext_send_data_q_3[127:0] =
		(ds_aes_retire_atag_3t3[5:0] == 6'd0)  ? {ext_rf_data00_b3_q[31:0],ext_rf_data00_b2_q[31:0],ext_rf_data00_b1_q[31:0],ext_rf_data00_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd1)  ? {ext_rf_data01_b3_q[31:0],ext_rf_data01_b2_q[31:0],ext_rf_data01_b1_q[31:0],ext_rf_data01_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd2)  ? {ext_rf_data02_b3_q[31:0],ext_rf_data02_b2_q[31:0],ext_rf_data02_b1_q[31:0],ext_rf_data02_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd3)  ? {ext_rf_data03_b3_q[31:0],ext_rf_data03_b2_q[31:0],ext_rf_data03_b1_q[31:0],ext_rf_data03_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd4)  ? {ext_rf_data04_b3_q[31:0],ext_rf_data04_b2_q[31:0],ext_rf_data04_b1_q[31:0],ext_rf_data04_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd5)  ? {ext_rf_data05_b3_q[31:0],ext_rf_data05_b2_q[31:0],ext_rf_data05_b1_q[31:0],ext_rf_data05_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd6)  ? {ext_rf_data06_b3_q[31:0],ext_rf_data06_b2_q[31:0],ext_rf_data06_b1_q[31:0],ext_rf_data06_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd7)  ? {ext_rf_data07_b3_q[31:0],ext_rf_data07_b2_q[31:0],ext_rf_data07_b1_q[31:0],ext_rf_data07_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd8)  ? {ext_rf_data08_b3_q[31:0],ext_rf_data08_b2_q[31:0],ext_rf_data08_b1_q[31:0],ext_rf_data08_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd9)  ? {ext_rf_data09_b3_q[31:0],ext_rf_data09_b2_q[31:0],ext_rf_data09_b1_q[31:0],ext_rf_data09_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd10) ? {ext_rf_data10_b3_q[31:0],ext_rf_data10_b2_q[31:0],ext_rf_data10_b1_q[31:0],ext_rf_data10_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd11) ? {ext_rf_data11_b3_q[31:0],ext_rf_data11_b2_q[31:0],ext_rf_data11_b1_q[31:0],ext_rf_data11_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd12) ? {ext_rf_data12_b3_q[31:0],ext_rf_data12_b2_q[31:0],ext_rf_data12_b1_q[31:0],ext_rf_data12_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd13) ? {ext_rf_data13_b3_q[31:0],ext_rf_data13_b2_q[31:0],ext_rf_data13_b1_q[31:0],ext_rf_data13_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd14) ? {ext_rf_data14_b3_q[31:0],ext_rf_data14_b2_q[31:0],ext_rf_data14_b1_q[31:0],ext_rf_data14_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd15) ? {ext_rf_data15_b3_q[31:0],ext_rf_data15_b2_q[31:0],ext_rf_data15_b1_q[31:0],ext_rf_data15_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd16) ? {ext_rf_data16_b3_q[31:0],ext_rf_data16_b2_q[31:0],ext_rf_data16_b1_q[31:0],ext_rf_data16_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd17) ? {ext_rf_data17_b3_q[31:0],ext_rf_data17_b2_q[31:0],ext_rf_data17_b1_q[31:0],ext_rf_data17_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd18) ? {ext_rf_data18_b3_q[31:0],ext_rf_data18_b2_q[31:0],ext_rf_data18_b1_q[31:0],ext_rf_data18_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd19) ? {ext_rf_data19_b3_q[31:0],ext_rf_data19_b2_q[31:0],ext_rf_data19_b1_q[31:0],ext_rf_data19_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd20) ? {ext_rf_data20_b3_q[31:0],ext_rf_data20_b2_q[31:0],ext_rf_data20_b1_q[31:0],ext_rf_data20_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd21) ? {ext_rf_data21_b3_q[31:0],ext_rf_data21_b2_q[31:0],ext_rf_data21_b1_q[31:0],ext_rf_data21_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd22) ? {ext_rf_data22_b3_q[31:0],ext_rf_data22_b2_q[31:0],ext_rf_data22_b1_q[31:0],ext_rf_data22_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd23) ? {ext_rf_data23_b3_q[31:0],ext_rf_data23_b2_q[31:0],ext_rf_data23_b1_q[31:0],ext_rf_data23_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd24) ? {ext_rf_data24_b3_q[31:0],ext_rf_data24_b2_q[31:0],ext_rf_data24_b1_q[31:0],ext_rf_data24_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd25) ? {ext_rf_data25_b3_q[31:0],ext_rf_data25_b2_q[31:0],ext_rf_data25_b1_q[31:0],ext_rf_data25_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd26) ? {ext_rf_data26_b3_q[31:0],ext_rf_data26_b2_q[31:0],ext_rf_data26_b1_q[31:0],ext_rf_data26_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd27) ? {ext_rf_data27_b3_q[31:0],ext_rf_data27_b2_q[31:0],ext_rf_data27_b1_q[31:0],ext_rf_data27_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd28) ? {ext_rf_data28_b3_q[31:0],ext_rf_data28_b2_q[31:0],ext_rf_data28_b1_q[31:0],ext_rf_data28_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd29) ? {ext_rf_data29_b3_q[31:0],ext_rf_data29_b2_q[31:0],ext_rf_data29_b1_q[31:0],ext_rf_data29_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd30) ? {ext_rf_data30_b3_q[31:0],ext_rf_data30_b2_q[31:0],ext_rf_data30_b1_q[31:0],ext_rf_data30_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd31) ? {ext_rf_data31_b3_q[31:0],ext_rf_data31_b2_q[31:0],ext_rf_data31_b1_q[31:0],ext_rf_data31_b0_q[31:0]} :
		(ds_aes_retire_atag_3t3[5:0] == 6'd32) ? {ext_rf_data32_b3_q[31:0],ext_rf_data32_b2_q[31:0],ext_rf_data32_b1_q[31:0],ext_rf_data32_b0_q[31:0]} :
		{ext_rf_data33_b3_q[31:0],ext_rf_data33_b2_q[31:0],ext_rf_data33_b1_q[31:0],ext_rf_data33_b0_q[31:0]};
	
	assign ext_send_data_q_4[127:0] =
		(ds_aes_retire_atag_4t3[5:0] == 6'd0)  ? {ext_rf_data00_b3_q[31:0],ext_rf_data00_b2_q[31:0],ext_rf_data00_b1_q[31:0],ext_rf_data00_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd1)  ? {ext_rf_data01_b3_q[31:0],ext_rf_data01_b2_q[31:0],ext_rf_data01_b1_q[31:0],ext_rf_data01_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd2)  ? {ext_rf_data02_b3_q[31:0],ext_rf_data02_b2_q[31:0],ext_rf_data02_b1_q[31:0],ext_rf_data02_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd3)  ? {ext_rf_data03_b3_q[31:0],ext_rf_data03_b2_q[31:0],ext_rf_data03_b1_q[31:0],ext_rf_data03_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd4)  ? {ext_rf_data04_b3_q[31:0],ext_rf_data04_b2_q[31:0],ext_rf_data04_b1_q[31:0],ext_rf_data04_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd5)  ? {ext_rf_data05_b3_q[31:0],ext_rf_data05_b2_q[31:0],ext_rf_data05_b1_q[31:0],ext_rf_data05_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd6)  ? {ext_rf_data06_b3_q[31:0],ext_rf_data06_b2_q[31:0],ext_rf_data06_b1_q[31:0],ext_rf_data06_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd7)  ? {ext_rf_data07_b3_q[31:0],ext_rf_data07_b2_q[31:0],ext_rf_data07_b1_q[31:0],ext_rf_data07_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd8)  ? {ext_rf_data08_b3_q[31:0],ext_rf_data08_b2_q[31:0],ext_rf_data08_b1_q[31:0],ext_rf_data08_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd9)  ? {ext_rf_data09_b3_q[31:0],ext_rf_data09_b2_q[31:0],ext_rf_data09_b1_q[31:0],ext_rf_data09_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd10) ? {ext_rf_data10_b3_q[31:0],ext_rf_data10_b2_q[31:0],ext_rf_data10_b1_q[31:0],ext_rf_data10_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd11) ? {ext_rf_data11_b3_q[31:0],ext_rf_data11_b2_q[31:0],ext_rf_data11_b1_q[31:0],ext_rf_data11_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd12) ? {ext_rf_data12_b3_q[31:0],ext_rf_data12_b2_q[31:0],ext_rf_data12_b1_q[31:0],ext_rf_data12_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd13) ? {ext_rf_data13_b3_q[31:0],ext_rf_data13_b2_q[31:0],ext_rf_data13_b1_q[31:0],ext_rf_data13_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd14) ? {ext_rf_data14_b3_q[31:0],ext_rf_data14_b2_q[31:0],ext_rf_data14_b1_q[31:0],ext_rf_data14_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd15) ? {ext_rf_data15_b3_q[31:0],ext_rf_data15_b2_q[31:0],ext_rf_data15_b1_q[31:0],ext_rf_data15_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd16) ? {ext_rf_data16_b3_q[31:0],ext_rf_data16_b2_q[31:0],ext_rf_data16_b1_q[31:0],ext_rf_data16_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd17) ? {ext_rf_data17_b3_q[31:0],ext_rf_data17_b2_q[31:0],ext_rf_data17_b1_q[31:0],ext_rf_data17_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd18) ? {ext_rf_data18_b3_q[31:0],ext_rf_data18_b2_q[31:0],ext_rf_data18_b1_q[31:0],ext_rf_data18_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd19) ? {ext_rf_data19_b3_q[31:0],ext_rf_data19_b2_q[31:0],ext_rf_data19_b1_q[31:0],ext_rf_data19_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd20) ? {ext_rf_data20_b3_q[31:0],ext_rf_data20_b2_q[31:0],ext_rf_data20_b1_q[31:0],ext_rf_data20_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd21) ? {ext_rf_data21_b3_q[31:0],ext_rf_data21_b2_q[31:0],ext_rf_data21_b1_q[31:0],ext_rf_data21_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd22) ? {ext_rf_data22_b3_q[31:0],ext_rf_data22_b2_q[31:0],ext_rf_data22_b1_q[31:0],ext_rf_data22_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd23) ? {ext_rf_data23_b3_q[31:0],ext_rf_data23_b2_q[31:0],ext_rf_data23_b1_q[31:0],ext_rf_data23_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd24) ? {ext_rf_data24_b3_q[31:0],ext_rf_data24_b2_q[31:0],ext_rf_data24_b1_q[31:0],ext_rf_data24_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd25) ? {ext_rf_data25_b3_q[31:0],ext_rf_data25_b2_q[31:0],ext_rf_data25_b1_q[31:0],ext_rf_data25_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd26) ? {ext_rf_data26_b3_q[31:0],ext_rf_data26_b2_q[31:0],ext_rf_data26_b1_q[31:0],ext_rf_data26_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd27) ? {ext_rf_data27_b3_q[31:0],ext_rf_data27_b2_q[31:0],ext_rf_data27_b1_q[31:0],ext_rf_data27_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd28) ? {ext_rf_data28_b3_q[31:0],ext_rf_data28_b2_q[31:0],ext_rf_data28_b1_q[31:0],ext_rf_data28_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd29) ? {ext_rf_data29_b3_q[31:0],ext_rf_data29_b2_q[31:0],ext_rf_data29_b1_q[31:0],ext_rf_data29_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd30) ? {ext_rf_data30_b3_q[31:0],ext_rf_data30_b2_q[31:0],ext_rf_data30_b1_q[31:0],ext_rf_data30_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd31) ? {ext_rf_data31_b3_q[31:0],ext_rf_data31_b2_q[31:0],ext_rf_data31_b1_q[31:0],ext_rf_data31_b0_q[31:0]} :
		(ds_aes_retire_atag_4t3[5:0] == 6'd32) ? {ext_rf_data32_b3_q[31:0],ext_rf_data32_b2_q[31:0],ext_rf_data32_b1_q[31:0],ext_rf_data32_b0_q[31:0]} :
		{ext_rf_data33_b3_q[31:0],ext_rf_data33_b2_q[31:0],ext_rf_data33_b1_q[31:0],ext_rf_data33_b0_q[31:0]};
	
	assign ext_send_data_q_5[127:0] =
		(ds_aes_retire_atag_5t3[5:0] == 6'd0)  ? {ext_rf_data00_b3_q[31:0],ext_rf_data00_b2_q[31:0],ext_rf_data00_b1_q[31:0],ext_rf_data00_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd1)  ? {ext_rf_data01_b3_q[31:0],ext_rf_data01_b2_q[31:0],ext_rf_data01_b1_q[31:0],ext_rf_data01_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd2)  ? {ext_rf_data02_b3_q[31:0],ext_rf_data02_b2_q[31:0],ext_rf_data02_b1_q[31:0],ext_rf_data02_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd3)  ? {ext_rf_data03_b3_q[31:0],ext_rf_data03_b2_q[31:0],ext_rf_data03_b1_q[31:0],ext_rf_data03_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd4)  ? {ext_rf_data04_b3_q[31:0],ext_rf_data04_b2_q[31:0],ext_rf_data04_b1_q[31:0],ext_rf_data04_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd5)  ? {ext_rf_data05_b3_q[31:0],ext_rf_data05_b2_q[31:0],ext_rf_data05_b1_q[31:0],ext_rf_data05_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd6)  ? {ext_rf_data06_b3_q[31:0],ext_rf_data06_b2_q[31:0],ext_rf_data06_b1_q[31:0],ext_rf_data06_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd7)  ? {ext_rf_data07_b3_q[31:0],ext_rf_data07_b2_q[31:0],ext_rf_data07_b1_q[31:0],ext_rf_data07_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd8)  ? {ext_rf_data08_b3_q[31:0],ext_rf_data08_b2_q[31:0],ext_rf_data08_b1_q[31:0],ext_rf_data08_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd9)  ? {ext_rf_data09_b3_q[31:0],ext_rf_data09_b2_q[31:0],ext_rf_data09_b1_q[31:0],ext_rf_data09_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd10) ? {ext_rf_data10_b3_q[31:0],ext_rf_data10_b2_q[31:0],ext_rf_data10_b1_q[31:0],ext_rf_data10_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd11) ? {ext_rf_data11_b3_q[31:0],ext_rf_data11_b2_q[31:0],ext_rf_data11_b1_q[31:0],ext_rf_data11_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd12) ? {ext_rf_data12_b3_q[31:0],ext_rf_data12_b2_q[31:0],ext_rf_data12_b1_q[31:0],ext_rf_data12_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd13) ? {ext_rf_data13_b3_q[31:0],ext_rf_data13_b2_q[31:0],ext_rf_data13_b1_q[31:0],ext_rf_data13_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd14) ? {ext_rf_data14_b3_q[31:0],ext_rf_data14_b2_q[31:0],ext_rf_data14_b1_q[31:0],ext_rf_data14_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd15) ? {ext_rf_data15_b3_q[31:0],ext_rf_data15_b2_q[31:0],ext_rf_data15_b1_q[31:0],ext_rf_data15_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd16) ? {ext_rf_data16_b3_q[31:0],ext_rf_data16_b2_q[31:0],ext_rf_data16_b1_q[31:0],ext_rf_data16_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd17) ? {ext_rf_data17_b3_q[31:0],ext_rf_data17_b2_q[31:0],ext_rf_data17_b1_q[31:0],ext_rf_data17_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd18) ? {ext_rf_data18_b3_q[31:0],ext_rf_data18_b2_q[31:0],ext_rf_data18_b1_q[31:0],ext_rf_data18_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd19) ? {ext_rf_data19_b3_q[31:0],ext_rf_data19_b2_q[31:0],ext_rf_data19_b1_q[31:0],ext_rf_data19_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd20) ? {ext_rf_data20_b3_q[31:0],ext_rf_data20_b2_q[31:0],ext_rf_data20_b1_q[31:0],ext_rf_data20_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd21) ? {ext_rf_data21_b3_q[31:0],ext_rf_data21_b2_q[31:0],ext_rf_data21_b1_q[31:0],ext_rf_data21_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd22) ? {ext_rf_data22_b3_q[31:0],ext_rf_data22_b2_q[31:0],ext_rf_data22_b1_q[31:0],ext_rf_data22_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd23) ? {ext_rf_data23_b3_q[31:0],ext_rf_data23_b2_q[31:0],ext_rf_data23_b1_q[31:0],ext_rf_data23_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd24) ? {ext_rf_data24_b3_q[31:0],ext_rf_data24_b2_q[31:0],ext_rf_data24_b1_q[31:0],ext_rf_data24_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd25) ? {ext_rf_data25_b3_q[31:0],ext_rf_data25_b2_q[31:0],ext_rf_data25_b1_q[31:0],ext_rf_data25_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd26) ? {ext_rf_data26_b3_q[31:0],ext_rf_data26_b2_q[31:0],ext_rf_data26_b1_q[31:0],ext_rf_data26_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd27) ? {ext_rf_data27_b3_q[31:0],ext_rf_data27_b2_q[31:0],ext_rf_data27_b1_q[31:0],ext_rf_data27_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd28) ? {ext_rf_data28_b3_q[31:0],ext_rf_data28_b2_q[31:0],ext_rf_data28_b1_q[31:0],ext_rf_data28_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd29) ? {ext_rf_data29_b3_q[31:0],ext_rf_data29_b2_q[31:0],ext_rf_data29_b1_q[31:0],ext_rf_data29_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd30) ? {ext_rf_data30_b3_q[31:0],ext_rf_data30_b2_q[31:0],ext_rf_data30_b1_q[31:0],ext_rf_data30_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd31) ? {ext_rf_data31_b3_q[31:0],ext_rf_data31_b2_q[31:0],ext_rf_data31_b1_q[31:0],ext_rf_data31_b0_q[31:0]} :
		(ds_aes_retire_atag_5t3[5:0] == 6'd32) ? {ext_rf_data32_b3_q[31:0],ext_rf_data32_b2_q[31:0],ext_rf_data32_b1_q[31:0],ext_rf_data32_b0_q[31:0]} :
		{ext_rf_data33_b3_q[31:0],ext_rf_data33_b2_q[31:0],ext_rf_data33_b1_q[31:0],ext_rf_data33_b0_q[31:0]};
	
	
	assign ext_send_data_0[31:0] = ds_aes_retire_atag_0t3[7:6] == 2'b11 ? ext_send_data_q_0[127:96] :
		ds_aes_retire_atag_0t3[7:6] == 2'b10 ? ext_send_data_q_0[95:64] :
		ds_aes_retire_atag_0t3[7:6] == 2'b01 ? ext_send_data_q_0[63:32] :
		ext_send_data_q_0[31:0];
	assign ext_send_data_1[31:0] = ds_aes_retire_atag_1t3[7:6] == 2'b11 ? ext_send_data_q_1[127:96] :
		ds_aes_retire_atag_1t3[7:6] == 2'b10 ? ext_send_data_q_1[95:64] :
		ds_aes_retire_atag_1t3[7:6] == 2'b01 ? ext_send_data_q_1[63:32] :
		ext_send_data_q_1[31:0];
	assign ext_send_data_2[31:0] = ds_aes_retire_atag_2t3[7:6] == 2'b11 ? ext_send_data_q_2[127:96] :
		ds_aes_retire_atag_2t3[7:6] == 2'b10 ? ext_send_data_q_2[95:64] :
		ds_aes_retire_atag_2t3[7:6] == 2'b01 ? ext_send_data_q_2[63:32] :
		ext_send_data_q_2[31:0];
	assign ext_send_data_3[31:0] = ds_aes_retire_atag_3t3[7:6] == 2'b11 ? ext_send_data_q_3[127:96] :
		ds_aes_retire_atag_3t3[7:6] == 2'b10 ? ext_send_data_q_3[95:64] :
		ds_aes_retire_atag_3t3[7:6] == 2'b01 ? ext_send_data_q_3[63:32] :
		ext_send_data_q_3[31:0];
	assign ext_send_data_4[31:0] = ds_aes_retire_atag_4t3[7:6] == 2'b11 ? ext_send_data_q_4[127:96] :
		ds_aes_retire_atag_4t3[7:6] == 2'b10 ? ext_send_data_q_4[95:64] :
		ds_aes_retire_atag_4t3[7:6] == 2'b01 ? ext_send_data_q_4[63:32] :
		ext_send_data_q_4[31:0];
	assign ext_send_data_5[31:0] = ds_aes_retire_atag_5t3[7:6] == 2'b11 ? ext_send_data_q_5[127:96] :
		ds_aes_retire_atag_5t3[7:6] == 2'b10 ? ext_send_data_q_5[95:64] :
		ds_aes_retire_atag_5t3[7:6] == 2'b01 ? ext_send_data_q_5[63:32] :
		ext_send_data_q_5[31:0];
	
	assign aes_send_data_0[31:0] = aes_mask_0t3 ? aes_resq_ret_data_0t3_q :
		(ds_aes_retire_type_0t3[0] ? ext_send_data_0[31:0] : arm_send_data_0[31:0]);
	assign aes_send_data_1[31:0] = aes_mask_1t3 ? aes_resq_ret_data_1t3_q :
		(ds_aes_retire_type_1t3[0] ? ext_send_data_1[31:0] : arm_send_data_1[31:0]);
	assign aes_send_data_2[31:0] = aes_mask_2t3 ? aes_resq_ret_data_2t3_q :
		(ds_aes_retire_type_2t3[0] ? ext_send_data_2[31:0] : arm_send_data_2[31:0]);
	assign aes_send_data_3[31:0] = aes_mask_3t3 ? aes_resq_ret_data_3t3_q :
		(ds_aes_retire_type_3t3[0] ? ext_send_data_3[31:0] : arm_send_data_3[31:0]);
	assign aes_send_data_4[31:0] = aes_mask_4t3 ? aes_resq_ret_data_4t3_q :
		(ds_aes_retire_type_4t3[0] ? ext_send_data_4[31:0] : arm_send_data_4[31:0]);
	assign aes_send_data_5[31:0] = ds_aes_retire_type_5t3[0] ? ext_send_data_5[31:0] : arm_send_data_5[31:0];
	
	assign aes_mask_0t3 = (ds_aes_retire_vld_1t3 &&  ds_aes_retire_type_0t3[1:0]==ds_aes_retire_type_1t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_0t3[5:0]==ds_aes_retire_atag_1t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_0t3[7:6]==ds_aes_retire_atag_1t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_0t3[7:6]==2'b01 && ds_aes_retire_zbits_1t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_0t3[7:6]==2'b10 && ds_aes_retire_zbits_1t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_0t3[7:6]==2'b11 && ds_aes_retire_zbits_1t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		) ||
		(ds_aes_retire_vld_2t3 &&  ds_aes_retire_type_0t3[1:0]==ds_aes_retire_type_2t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_0t3[5:0]==ds_aes_retire_atag_2t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_0t3[7:6]==ds_aes_retire_atag_2t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_0t3[7:6]==2'b01 && ds_aes_retire_zbits_2t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_0t3[7:6]==2'b10 && ds_aes_retire_zbits_2t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_0t3[7:6]==2'b11 && ds_aes_retire_zbits_2t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		) ||
		(ds_aes_retire_vld_3t3 &&  ds_aes_retire_type_0t3[1:0]==ds_aes_retire_type_3t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_0t3[5:0]==ds_aes_retire_atag_3t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_0t3[7:6]==ds_aes_retire_atag_3t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_0t3[7:6]==2'b01 && ds_aes_retire_zbits_3t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_0t3[7:6]==2'b10 && ds_aes_retire_zbits_3t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_0t3[7:6]==2'b11 && ds_aes_retire_zbits_3t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		) ||
		(ds_aes_retire_vld_4t3 &&  ds_aes_retire_type_0t3[1:0]==ds_aes_retire_type_4t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_0t3[5:0]==ds_aes_retire_atag_4t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_0t3[7:6]==ds_aes_retire_atag_4t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_0t3[7:6]==2'b01 && ds_aes_retire_zbits_4t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_0t3[7:6]==2'b10 && ds_aes_retire_zbits_4t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_0t3[7:6]==2'b11 && ds_aes_retire_zbits_4t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		) ||
		(ds_aes_retire_vld_5t3 &&  ds_aes_retire_type_0t3[1:0]==ds_aes_retire_type_5t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_0t3[5:0]==ds_aes_retire_atag_5t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_0t3[7:6]==ds_aes_retire_atag_5t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_0t3[7:6]==2'b01 && ds_aes_retire_zbits_5t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_0t3[7:6]==2'b10 && ds_aes_retire_zbits_5t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_0t3[7:6]==2'b11 && ds_aes_retire_zbits_5t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		);
	
	assign aes_mask_1t3 = (ds_aes_retire_vld_2t3 &&  ds_aes_retire_type_1t3[1:0]==ds_aes_retire_type_2t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_1t3[5:0]==ds_aes_retire_atag_2t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_1t3[7:6]==ds_aes_retire_atag_2t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_1t3[7:6]==2'b01 && ds_aes_retire_zbits_2t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_1t3[7:6]==2'b10 && ds_aes_retire_zbits_2t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_1t3[7:6]==2'b11 && ds_aes_retire_zbits_2t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		) ||
		(ds_aes_retire_vld_3t3 &&  ds_aes_retire_type_1t3[1:0]==ds_aes_retire_type_3t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_1t3[5:0]==ds_aes_retire_atag_3t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_1t3[7:6]==ds_aes_retire_atag_3t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_1t3[7:6]==2'b01 && ds_aes_retire_zbits_3t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_1t3[7:6]==2'b10 && ds_aes_retire_zbits_3t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_1t3[7:6]==2'b11 && ds_aes_retire_zbits_3t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		) ||
		(ds_aes_retire_vld_4t3 &&  ds_aes_retire_type_1t3[1:0]==ds_aes_retire_type_4t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_1t3[5:0]==ds_aes_retire_atag_4t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_1t3[7:6]==ds_aes_retire_atag_4t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_1t3[7:6]==2'b01 && ds_aes_retire_zbits_4t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_1t3[7:6]==2'b10 && ds_aes_retire_zbits_4t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_1t3[7:6]==2'b11 && ds_aes_retire_zbits_4t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		) ||
		(ds_aes_retire_vld_5t3 &&  ds_aes_retire_type_1t3[1:0]==ds_aes_retire_type_5t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_1t3[5:0]==ds_aes_retire_atag_5t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_1t3[7:6]==ds_aes_retire_atag_5t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_1t3[7:6]==2'b01 && ds_aes_retire_zbits_5t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_1t3[7:6]==2'b10 && ds_aes_retire_zbits_5t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_1t3[7:6]==2'b11 && ds_aes_retire_zbits_5t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		);
	
	
	assign aes_mask_2t3 = (ds_aes_retire_vld_3t3 &&  ds_aes_retire_type_2t3[1:0]==ds_aes_retire_type_3t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_2t3[5:0]==ds_aes_retire_atag_3t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_2t3[7:6]==ds_aes_retire_atag_3t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_2t3[7:6]==2'b01 && ds_aes_retire_zbits_3t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_2t3[7:6]==2'b10 && ds_aes_retire_zbits_3t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_2t3[7:6]==2'b11 && ds_aes_retire_zbits_3t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		) ||
		(ds_aes_retire_vld_4t3 &&  ds_aes_retire_type_2t3[1:0]==ds_aes_retire_type_4t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_2t3[5:0]==ds_aes_retire_atag_4t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_2t3[7:6]==ds_aes_retire_atag_4t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_2t3[7:6]==2'b01 && ds_aes_retire_zbits_4t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_2t3[7:6]==2'b10 && ds_aes_retire_zbits_4t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_2t3[7:6]==2'b11 && ds_aes_retire_zbits_4t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		) ||
		(ds_aes_retire_vld_5t3 &&  ds_aes_retire_type_2t3[1:0]==ds_aes_retire_type_5t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_2t3[5:0]==ds_aes_retire_atag_5t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_2t3[7:6]==ds_aes_retire_atag_5t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_2t3[7:6]==2'b01 && ds_aes_retire_zbits_5t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_2t3[7:6]==2'b10 && ds_aes_retire_zbits_5t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_2t3[7:6]==2'b11 && ds_aes_retire_zbits_5t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		);
	
	assign aes_mask_3t3 = (ds_aes_retire_vld_4t3 &&  ds_aes_retire_type_3t3[1:0]==ds_aes_retire_type_4t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_3t3[5:0]==ds_aes_retire_atag_4t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_3t3[7:6]==ds_aes_retire_atag_4t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_3t3[7:6]==2'b01 && ds_aes_retire_zbits_4t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_3t3[7:6]==2'b10 && ds_aes_retire_zbits_4t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_3t3[7:6]==2'b11 && ds_aes_retire_zbits_4t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		) ||
		(ds_aes_retire_vld_5t3 &&  ds_aes_retire_type_3t3[1:0]==ds_aes_retire_type_5t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_3t3[5:0]==ds_aes_retire_atag_5t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_3t3[7:6]==ds_aes_retire_atag_5t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_3t3[7:6]==2'b01 && ds_aes_retire_zbits_5t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_3t3[7:6]==2'b10 && ds_aes_retire_zbits_5t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_3t3[7:6]==2'b11 && ds_aes_retire_zbits_5t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		);
	
	assign aes_mask_4t3 = (ds_aes_retire_vld_5t3 &&  ds_aes_retire_type_4t3[1:0]==ds_aes_retire_type_5t3[1:0]  &&		//Both are ARM or EXT
		ds_aes_retire_atag_4t3[5:0]==ds_aes_retire_atag_5t3[5:0]  &&		//The same Architectural Register
		(ds_aes_retire_atag_4t3[7:6]==ds_aes_retire_atag_5t3[7:6]        ||		//Younger uOp will overwrite older uOp data(same bank)
		ds_aes_retire_atag_4t3[7:6]==2'b01 && ds_aes_retire_zbits_5t3[1] ||		//Younger uOp has Bank1 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_4t3[7:6]==2'b10 && ds_aes_retire_zbits_5t3[2] ||		//Younger uOp has Bank2 Zbit set which will zero-out older uOp data
		ds_aes_retire_atag_4t3[7:6]==2'b11 && ds_aes_retire_zbits_5t3[3]   )		//Younger uOp has Bank3 Zbit set which will zero-out older uOp data
		);
	
	
	assign aes_mask_5t3 = 1'b0;
	
	wire aes_send_vld_0t3;
	wire aes_send_vld_1t3;
	wire aes_send_vld_2t3;
	wire aes_send_vld_3t3;
	wire aes_send_vld_4t3;
	wire aes_send_vld_5t3;
	
	
	assign aes_send_vld_0t3 = ds_aes_retire_vld_0t3 && ((ds_aes_retire_type_0t3[1:0]==2'b00 &&
		ds_aes_retire_atag_0t3[5:1]!=5'b10100) ||		// ARM temps [5:0]=40,41(rows)
		(ds_aes_retire_type_0t3[1:0]==2'b01 &&
		ds_aes_retire_atag_0t3[5:1]!=5'b10000));		// EXT temps(rows 32,33)
	assign aes_send_vld_1t3 = ds_aes_retire_vld_1t3 && ((ds_aes_retire_type_1t3[1:0]==2'b00 &&
		ds_aes_retire_atag_1t3[5:1]!=5'b10100) ||		// ARM temps [5:0]=40,41
		(ds_aes_retire_type_1t3[1:0]==2'b01 &&
		ds_aes_retire_atag_1t3[5:1]!=5'b10000));		// EXT temps(rows 32,33)
	assign aes_send_vld_2t3 = ds_aes_retire_vld_2t3 && ((ds_aes_retire_type_2t3[1:0]==2'b00 &&
		ds_aes_retire_atag_2t3[5:1]!=5'b10100) ||		// ARM temps [5:0]=40,41
		(ds_aes_retire_type_2t3[1:0]==2'b01 &&
		ds_aes_retire_atag_2t3[5:1]!=5'b10000));		// EXT temps(rows 32,33)
	assign aes_send_vld_3t3 = ds_aes_retire_vld_3t3 && ((ds_aes_retire_type_3t3[1:0]==2'b00 &&
		ds_aes_retire_atag_3t3[5:1]!=5'b10100) ||		// ARM temps [5:0]=40,41
		(ds_aes_retire_type_3t3[1:0]==2'b01 &&
		ds_aes_retire_atag_3t3[5:1]!=5'b10000));		// EXT temps(rows 32,33)
	assign aes_send_vld_4t3 = ds_aes_retire_vld_4t3 && ((ds_aes_retire_type_4t3[1:0]==2'b00 &&
		ds_aes_retire_atag_4t3[5:1]!=5'b10100) ||		// ARM temps [5:0]=40,41
		(ds_aes_retire_type_4t3[1:0]==2'b01 &&
		ds_aes_retire_atag_4t3[5:1]!=5'b10000));		// EXT temps(rows 32,33)
	assign aes_send_vld_5t3 = ds_aes_retire_vld_5t3 && ((ds_aes_retire_type_5t3[1:0]==2'b00 &&
		ds_aes_retire_atag_5t3[5:1]!=5'b10100) ||		// ARM temps [5:0]=40,41
		(ds_aes_retire_type_5t3[1:0]==2'b01 &&
		ds_aes_retire_atag_5t3[5:1]!=5'b10000));		// EXT temps(rows 32,33)
	
	
	
	reg       crypto_aes_vld_w1_q;
	reg       crypto_aes_vld_w2_q;
	reg       crypto_aes_vld_t1_q;
	reg       crypto_aes_vld_t2_q;
	reg       crypto_aes_vld_t3_q;
	reg       crypto_aese_e2_q;
	reg       crypto_aesd_e2_q;
	reg       crypto_aese_w1_q;
	reg       crypto_aesd_w1_q;
	reg [`XM_AES_RTAG_INDEX-1:0] crypto_rtag_e2_q;
	reg [`XM_AES_RTAG_INDEX-1:0] crypto_rtag_w1_q;
	reg [`XM_AES_RTAG_INDEX-1:0] crypto_rtag_w2_q;
	reg [`XM_AES_RTAG_INDEX-1:0] crypto_rtag_t1_q;
	reg [`XM_AES_RTAG_INDEX-1:0] crypto_rtag_t2_q;
	reg [`XM_AES_RTAG_INDEX-1:0] crypto_rtag_t3_q;
	reg [6:0] crypto_aes_gid_e2_q;
	reg [6:0] crypto_aes_gid_w1_q;
	reg [6:0] crypto_aes_gid_w2_q;
	reg [6:0] crypto_aes_gid_t1_q;
	reg [6:0] crypto_aes_gid_t2_q;
	reg [6:0] crypto_aes_gid_t3_q;
	reg [127:0]     crypto_aes_out_w1_q;
	reg [127:0]     crypto_aes_out_w2_q;
	reg [127:0]     crypto_aes_out_t1_q;
	reg [127:0]     crypto_aes_out_t2_q;
	reg [127:0]     crypto_aes_out_t3_q;
	wire      crypto_superop_e1_q;
	assign    crypto_superop_e1_q = ~crypto_op_type_e1_q[4] & crypto_op_type_e1_q[3] & crypto_op_type_e1_q[2] & ~crypto_op_type_e1_q[1];
	//The uop datapath control for the crypto unit (uop_ctl[58:34]) where
	//38:34 - 0_1100(AESE) and 0_1101(AESD)
	//31:   - Crypto2 Valid(indicate uop ctl is for a Crypto2 AESE/D)
	wire      fused_parent_jp2;
	assign    fused_parent_jp2 = ~dsu_vfu_uop_ctl_jp2[38] & dsu_vfu_uop_ctl_jp2[37] & dsu_vfu_uop_ctl_jp2[36] & ~dsu_vfu_uop_ctl_jp2[35] & dsu_vfu_uop_ctl_jp2[31];
	
	//Crypto2 Issue to WB path: e1->e2->e3/w1->w2->t1->t2->t3
	always @(posedge ck_gclkcr) begin
		if(reset) begin
			crypto_aese_w1_q <= 1'b0;
			crypto_aesd_w1_q <= 1'b0;
			crypto_aes_vld_w1_q <= 1'b0;
			crypto_aes_vld_w2_q <= 1'b0;
			crypto_aes_vld_t1_q <= 1'b0;
			crypto_aes_vld_t2_q <= 1'b0;
			crypto_aes_vld_t3_q <= 1'b0;
			crypto_rtag_e2_q <= 7'b0;
			crypto_rtag_w1_q <= 7'b0;
			crypto_rtag_w2_q <= 7'b0;
			crypto_rtag_t1_q <= 7'b0;
			crypto_rtag_t2_q <= 7'b0;
			crypto_rtag_t3_q <= 7'b0;
		end
		else begin
			//crypto_aese_e1_q and crypto_aesd_e1_q are qualifying signals for Fused AESE and AESD; not for regular AESE and AESD
			crypto_aese_e2_q <= crypto_aese_e1_q & crypto_superop_e1_q & crypto_aes_issued_e1_q;
			crypto_aesd_e2_q <= crypto_aesd_e1_q & crypto_superop_e1_q & crypto_aes_issued_e1_q;
			if(crypto_aes_vld_e2_q) begin
				crypto_aes_vld_w1_q <= crypto_aes_vld_e2_q & (crypto_aese_e2_q | crypto_aesd_e2_q)
					& ~(bru_flush & (((crypto_aes_gid_e2_q[6]^ bru_flush_gid[6])    && (bru_flush_gid[5:0]> crypto_aes_gid_e2_q[5:0])) ||
					((crypto_aes_gid_e2_q[6]==bru_flush_gid[6])    && (bru_flush_gid[5:0]<=crypto_aes_gid_e2_q[5:0]))))
					& ~(dsu_flush & (((crypto_aes_gid_e2_q[6]^ dsu_flush_gid[6])    && (dsu_flush_gid[5:0]> crypto_aes_gid_e2_q[5:0])) ||
					((crypto_aes_gid_e2_q[6]==dsu_flush_gid[6])    && (dsu_flush_gid[5:0]<=crypto_aes_gid_e2_q[5:0]))))
					& ~(flush_u1 & (((crypto_aes_gid_e2_q[6]^ flush_gid_u1[6]) && (flush_gid_u1[5:0]> crypto_aes_gid_e2_q[5:0])) ||
					((crypto_aes_gid_e2_q[6]==flush_gid_u1[6]) && (flush_gid_u1[5:0]<=crypto_aes_gid_e2_q[5:0]))))
					& ~(flush_u2 & (((crypto_aes_gid_e2_q[6]^ flush_gid_u2[6]) && (flush_gid_u2[5:0]> crypto_aes_gid_e2_q[5:0])) ||
					((crypto_aes_gid_e2_q[6]==flush_gid_u2[6]) && (flush_gid_u2[5:0]<=crypto_aes_gid_e2_q[5:0]))))
					& ~(flush_u3 & (((crypto_aes_gid_e2_q[6]^ flush_gid_u3[6]) && (flush_gid_u3[5:0]> crypto_aes_gid_e2_q[5:0])) ||
					((crypto_aes_gid_e2_q[6]==flush_gid_u3[6]) && (flush_gid_u3[5:0]<=crypto_aes_gid_e2_q[5:0]))))
					& ~(flush_u4 & (((crypto_aes_gid_e2_q[6]^ flush_gid_u4[6]) && (flush_gid_u4[5:0]> crypto_aes_gid_e2_q[5:0])) ||
					((crypto_aes_gid_e2_q[6]==flush_gid_u4[6]) && (flush_gid_u4[5:0]<=crypto_aes_gid_e2_q[5:0]))))
					& ~(flush_u5 & (((crypto_aes_gid_e2_q[6]^ flush_gid_u5[6]) && (flush_gid_u5[5:0]> crypto_aes_gid_e2_q[5:0])) ||
					((crypto_aes_gid_e2_q[6]==flush_gid_u5[6]) && (flush_gid_u5[5:0]<=crypto_aes_gid_e2_q[5:0]))))
					& ~(flush_u6 & (((crypto_aes_gid_e2_q[6]^ flush_gid_u6[6]) && (flush_gid_u6[5:0]> crypto_aes_gid_e2_q[5:0])) ||
					((crypto_aes_gid_e2_q[6]==flush_gid_u6[6]) && (flush_gid_u6[5:0]<=crypto_aes_gid_e2_q[5:0]))));
			end
			else begin
				crypto_aes_vld_w1_q <=0;
			end
			if(crypto_aes_vld_w1_q) begin
				crypto_aes_vld_w2_q <= crypto_aes_vld_w1_q
					& ~(bru_flush & (((crypto_aes_gid_w1_q[6]^ bru_flush_gid[6])    && (bru_flush_gid[5:0]> crypto_aes_gid_w1_q[5:0])) ||
					((crypto_aes_gid_w1_q[6]==bru_flush_gid[6])    && (bru_flush_gid[5:0]<=crypto_aes_gid_w1_q[5:0]))))
					& ~(dsu_flush & (((crypto_aes_gid_w1_q[6]^ dsu_flush_gid[6])    && (dsu_flush_gid[5:0]> crypto_aes_gid_w1_q[5:0])) ||
					((crypto_aes_gid_w1_q[6]==dsu_flush_gid[6])    && (dsu_flush_gid[5:0]<=crypto_aes_gid_w1_q[5:0]))))
					& ~(flush_u1 & (((crypto_aes_gid_w1_q[6]^ flush_gid_u1[6]) && (flush_gid_u1[5:0]> crypto_aes_gid_w1_q[5:0])) ||
					((crypto_aes_gid_w1_q[6]==flush_gid_u1[6]) && (flush_gid_u1[5:0]<=crypto_aes_gid_w1_q[5:0]))))
					& ~(flush_u2 & (((crypto_aes_gid_w1_q[6]^ flush_gid_u2[6]) && (flush_gid_u2[5:0]> crypto_aes_gid_w1_q[5:0])) ||
					((crypto_aes_gid_w1_q[6]==flush_gid_u2[6]) && (flush_gid_u2[5:0]<=crypto_aes_gid_w1_q[5:0]))))
					& ~(flush_u3 & (((crypto_aes_gid_w1_q[6]^ flush_gid_u3[6]) && (flush_gid_u3[5:0]> crypto_aes_gid_w1_q[5:0])) ||
					((crypto_aes_gid_w1_q[6]==flush_gid_u3[6]) && (flush_gid_u3[5:0]<=crypto_aes_gid_w1_q[5:0]))))
					& ~(flush_u4 & (((crypto_aes_gid_w1_q[6]^ flush_gid_u4[6]) && (flush_gid_u4[5:0]> crypto_aes_gid_w1_q[5:0])) ||
					((crypto_aes_gid_w1_q[6]==flush_gid_u4[6]) && (flush_gid_u4[5:0]<=crypto_aes_gid_w1_q[5:0]))))
					& ~(flush_u5 & (((crypto_aes_gid_w1_q[6]^ flush_gid_u5[6]) && (flush_gid_u5[5:0]> crypto_aes_gid_w1_q[5:0])) ||
					((crypto_aes_gid_w1_q[6]==flush_gid_u5[6]) && (flush_gid_u5[5:0]<=crypto_aes_gid_w1_q[5:0]))))
					& ~(flush_u6 & (((crypto_aes_gid_w1_q[6]^ flush_gid_u6[6]) && (flush_gid_u6[5:0]> crypto_aes_gid_w1_q[5:0])) ||
					((crypto_aes_gid_w1_q[6]==flush_gid_u6[6]) && (flush_gid_u6[5:0]<=crypto_aes_gid_w1_q[5:0]))));
			end
			else begin
				crypto_aes_vld_w2_q <=0;
			end
			if(crypto_aes_vld_w2_q) begin
				crypto_aes_vld_t1_q <= crypto_aes_vld_w2_q
					& ~(bru_flush & (((crypto_aes_gid_w2_q[6]^ bru_flush_gid[6])    && (bru_flush_gid[5:0]> crypto_aes_gid_w2_q[5:0])) ||
					((crypto_aes_gid_w2_q[6]==bru_flush_gid[6])    && (bru_flush_gid[5:0]<=crypto_aes_gid_w2_q[5:0]))))
					& ~(dsu_flush & (((crypto_aes_gid_w2_q[6]^ dsu_flush_gid[6])    && (dsu_flush_gid[5:0]> crypto_aes_gid_w2_q[5:0])) ||
					((crypto_aes_gid_w2_q[6]==dsu_flush_gid[6])    && (dsu_flush_gid[5:0]<=crypto_aes_gid_w2_q[5:0]))))
					& ~(flush_u1 & (((crypto_aes_gid_w2_q[6]^ flush_gid_u1[6]) && (flush_gid_u1[5:0]> crypto_aes_gid_w2_q[5:0])) ||
					((crypto_aes_gid_w2_q[6]==flush_gid_u1[6]) && (flush_gid_u1[5:0]<=crypto_aes_gid_w2_q[5:0]))))
					& ~(flush_u2 & (((crypto_aes_gid_w2_q[6]^ flush_gid_u2[6]) && (flush_gid_u2[5:0]> crypto_aes_gid_w2_q[5:0])) ||
					((crypto_aes_gid_w2_q[6]==flush_gid_u2[6]) && (flush_gid_u2[5:0]<=crypto_aes_gid_w2_q[5:0]))))
					& ~(flush_u3 & (((crypto_aes_gid_w2_q[6]^ flush_gid_u3[6]) && (flush_gid_u3[5:0]> crypto_aes_gid_w2_q[5:0])) ||
					((crypto_aes_gid_w2_q[6]==flush_gid_u3[6]) && (flush_gid_u3[5:0]<=crypto_aes_gid_w2_q[5:0]))))
					& ~(flush_u4 & (((crypto_aes_gid_w2_q[6]^ flush_gid_u4[6]) && (flush_gid_u4[5:0]> crypto_aes_gid_w2_q[5:0])) ||
					((crypto_aes_gid_w2_q[6]==flush_gid_u4[6]) && (flush_gid_u4[5:0]<=crypto_aes_gid_w2_q[5:0]))))
					& ~(flush_u5 & (((crypto_aes_gid_w2_q[6]^ flush_gid_u5[6]) && (flush_gid_u5[5:0]> crypto_aes_gid_w2_q[5:0])) ||
					((crypto_aes_gid_w2_q[6]==flush_gid_u5[6]) && (flush_gid_u5[5:0]<=crypto_aes_gid_w2_q[5:0]))))
					& ~(flush_u6 & (((crypto_aes_gid_w2_q[6]^ flush_gid_u6[6]) && (flush_gid_u6[5:0]> crypto_aes_gid_w2_q[5:0])) ||
					((crypto_aes_gid_w2_q[6]==flush_gid_u6[6]) && (flush_gid_u6[5:0]<=crypto_aes_gid_w2_q[5:0]))));
			end
			else begin
				crypto_aes_vld_t1_q <=0;
			end
			if(crypto_aes_vld_t1_q) begin
				crypto_aes_vld_t2_q <= crypto_aes_vld_t1_q
					& ~(bru_flush & (((crypto_aes_gid_t1_q[6]^ bru_flush_gid[6])    && (bru_flush_gid[5:0]> crypto_aes_gid_t1_q[5:0])) ||
					((crypto_aes_gid_t1_q[6]==bru_flush_gid[6])    && (bru_flush_gid[5:0]<=crypto_aes_gid_t1_q[5:0]))))
					& ~(dsu_flush & (((crypto_aes_gid_t1_q[6]^ dsu_flush_gid[6])    && (dsu_flush_gid[5:0]> crypto_aes_gid_t1_q[5:0])) ||
					((crypto_aes_gid_t1_q[6]==dsu_flush_gid[6])    && (dsu_flush_gid[5:0]<=crypto_aes_gid_t1_q[5:0]))))
					& ~(flush_u1 & (((crypto_aes_gid_t1_q[6]^ flush_gid_u1[6]) && (flush_gid_u1[5:0]> crypto_aes_gid_t1_q[5:0])) ||
					((crypto_aes_gid_t1_q[6]==flush_gid_u1[6]) && (flush_gid_u1[5:0]<=crypto_aes_gid_t1_q[5:0]))))
					& ~(flush_u2 & (((crypto_aes_gid_t1_q[6]^ flush_gid_u2[6]) && (flush_gid_u2[5:0]> crypto_aes_gid_t1_q[5:0])) ||
					((crypto_aes_gid_t1_q[6]==flush_gid_u2[6]) && (flush_gid_u2[5:0]<=crypto_aes_gid_t1_q[5:0]))))
					& ~(flush_u3 & (((crypto_aes_gid_t1_q[6]^ flush_gid_u3[6]) && (flush_gid_u3[5:0]> crypto_aes_gid_t1_q[5:0])) ||
					((crypto_aes_gid_t1_q[6]==flush_gid_u3[6]) && (flush_gid_u3[5:0]<=crypto_aes_gid_t1_q[5:0]))))
					& ~(flush_u4 & (((crypto_aes_gid_t1_q[6]^ flush_gid_u4[6]) && (flush_gid_u4[5:0]> crypto_aes_gid_t1_q[5:0])) ||
					((crypto_aes_gid_t1_q[6]==flush_gid_u4[6]) && (flush_gid_u4[5:0]<=crypto_aes_gid_t1_q[5:0]))))
					& ~(flush_u5 & (((crypto_aes_gid_t1_q[6]^ flush_gid_u5[6]) && (flush_gid_u5[5:0]> crypto_aes_gid_t1_q[5:0])) ||
					((crypto_aes_gid_t1_q[6]==flush_gid_u5[6]) && (flush_gid_u5[5:0]<=crypto_aes_gid_t1_q[5:0]))))
					& ~(flush_u6 & (((crypto_aes_gid_t1_q[6]^ flush_gid_u6[6]) && (flush_gid_u6[5:0]> crypto_aes_gid_t1_q[5:0])) ||
					((crypto_aes_gid_t1_q[6]==flush_gid_u6[6]) && (flush_gid_u6[5:0]<=crypto_aes_gid_t1_q[5:0]))));
			end
			else begin
				crypto_aes_vld_t2_q <=0;
			end
			if(crypto_aes_vld_t2_q) begin
				//crypto_aes_vld_t3_q <= crypto_aes_vld_t2_q
				//Keep this code here for reference. The imm result is now calculated in C/C++
				crypto_aes_vld_t3_q <= 1'b0
					& ~(bru_flush & (((crypto_aes_gid_t2_q[6]^ bru_flush_gid[6])    && (bru_flush_gid[5:0]> crypto_aes_gid_t2_q[5:0])) ||
					((crypto_aes_gid_t2_q[6]==bru_flush_gid[6])    && (bru_flush_gid[5:0]<=crypto_aes_gid_t2_q[5:0]))))
					& ~(dsu_flush & (((crypto_aes_gid_t2_q[6]^ dsu_flush_gid[6])    && (dsu_flush_gid[5:0]> crypto_aes_gid_t2_q[5:0])) ||
					((crypto_aes_gid_t2_q[6]==dsu_flush_gid[6])    && (dsu_flush_gid[5:0]<=crypto_aes_gid_t2_q[5:0]))))
					& ~(flush_u1 & (((crypto_aes_gid_t2_q[6]^ flush_gid_u1[6]) && (flush_gid_u1[5:0]> crypto_aes_gid_t2_q[5:0])) ||
					((crypto_aes_gid_t2_q[6]==flush_gid_u1[6]) && (flush_gid_u1[5:0]<=crypto_aes_gid_t2_q[5:0]))))
					& ~(flush_u2 & (((crypto_aes_gid_t2_q[6]^ flush_gid_u2[6]) && (flush_gid_u2[5:0]> crypto_aes_gid_t2_q[5:0])) ||
					((crypto_aes_gid_t2_q[6]==flush_gid_u2[6]) && (flush_gid_u2[5:0]<=crypto_aes_gid_t2_q[5:0]))))
					& ~(flush_u3 & (((crypto_aes_gid_t2_q[6]^ flush_gid_u3[6]) && (flush_gid_u3[5:0]> crypto_aes_gid_t2_q[5:0])) ||
					((crypto_aes_gid_t2_q[6]==flush_gid_u3[6]) && (flush_gid_u3[5:0]<=crypto_aes_gid_t2_q[5:0]))))
					& ~(flush_u4 & (((crypto_aes_gid_t2_q[6]^ flush_gid_u4[6]) && (flush_gid_u4[5:0]> crypto_aes_gid_t2_q[5:0])) ||
					((crypto_aes_gid_t2_q[6]==flush_gid_u4[6]) && (flush_gid_u4[5:0]<=crypto_aes_gid_t2_q[5:0]))))
					& ~(flush_u5 & (((crypto_aes_gid_t2_q[6]^ flush_gid_u5[6]) && (flush_gid_u5[5:0]> crypto_aes_gid_t2_q[5:0])) ||
					((crypto_aes_gid_t2_q[6]==flush_gid_u5[6]) && (flush_gid_u5[5:0]<=crypto_aes_gid_t2_q[5:0]))))
					& ~(flush_u6 & (((crypto_aes_gid_t2_q[6]^ flush_gid_u6[6]) && (flush_gid_u6[5:0]> crypto_aes_gid_t2_q[5:0])) ||
					((crypto_aes_gid_t2_q[6]==flush_gid_u6[6]) && (flush_gid_u6[5:0]<=crypto_aes_gid_t2_q[5:0]))));
			end
			else begin
				crypto_aes_vld_t3_q <=0;
			end
			crypto_rtag_e2_q <= crypto_rtag_e1_q;
			crypto_rtag_w1_q <= crypto_rtag_e2_q;
			crypto_rtag_w2_q <= crypto_rtag_w1_q;
			crypto_rtag_t1_q <= crypto_rtag_w2_q;
			crypto_rtag_t2_q <= crypto_rtag_t1_q;
			crypto_rtag_t3_q <= crypto_rtag_t2_q;
			crypto_aes_gid_e2_q <= crypto_aes_gid_e1_q;
			crypto_aes_gid_w1_q <= crypto_aes_gid_e2_q;
			crypto_aes_gid_w2_q <= crypto_aes_gid_w1_q;
			crypto_aes_gid_t1_q <= crypto_aes_gid_w2_q;
			crypto_aes_gid_t2_q <= crypto_aes_gid_t1_q;
			crypto_aes_gid_t3_q <= crypto_aes_gid_t2_q;
			crypto_aes_out_w1_q <= crypto_aes_vld_e2_q ? crypto_aese_e2_q ? crypto_aese_out_e2_q : crypto_aesd_out_e2_q
				: crypto_aes_out_w1_q;
			crypto_aes_out_w2_q <= crypto_aes_out_w1_q;
			crypto_aes_out_t1_q <= crypto_aes_out_w2_q;
			crypto_aes_out_t2_q <= crypto_aes_out_t1_q;
			crypto_aes_out_t3_q <= crypto_aes_out_t2_q;
		end
	end
	
	////---------------------- Revised by sbc@2014-04-09 08:55 BEGIN----------------------

	`ifdef RAVEN_COSIM
	reg [511:0] aes_buff0;
	reg [511:0] aes_buff1;
	reg [511:0] aes_buff2;
	reg [511:0] aes_buff3;
	reg [511:0] aes_buff4;
	reg [511:0] aes_buff5;
	int 	      aes_flag0;
	int 	      aes_flag1;
	int 	      aes_flag2;
	int 	      aes_flag3;
	int 	      aes_flag4;
	int 	      aes_flag5;
	
	`endif // RAVEN_COSIM

	////---------------------- Revised by sbc@2014-04-09 08:56 END------------------------
	
	// always @ (posedge ck_gclkcr)
	// 	begin
	// 		if ( !reset )
	// 		begin
				
	// 			// NOTE: If you change the amount of data sent using AES_SEND
	// 			// then you must resize the scemi_output_pipe declaration,
	// 			// otherwise Bad Things will happen that are hard to debug.
				
	// 			if ( aes_send_vld_0t3)
	// 			begin
	// 				`AES_SEND({
	// 				aes_send_data_0,		// 32 bits of data
					
	// 				8'h00,		//   8 bits pad                            <--------32bit boundary
	// 				ds_aes_retire_zbits_0t3[3:0],		//  4 bits of zbit info
	// 				ds_aes_retire_dw_0t3,		//  1 bit of DW info
	// 				ds_aes_retire_type_0t3[2:0],		//  3 bits of type info
					
	// 				1'b0,		//  1 bit - no need to mask now
	// 				ds_aes_retire_rtag_0t3[6:0],		//  7 bits of rtag info
					
	// 				ds_aes_retire_atag_0t3[7:0],		//  8 bits of atag info
					

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 				clusterid,
	// 				2'b00,		//  2 bits pad
	// 				cpuid,		//  2 bits for cpuid
	// 				`T_AES,					//  4 bits type
					
	// 				cycle[31:0]		// 32 bit cycle count
	// 				});		// total   96 bits = 12 bytes
				
				
	// 		end
			
	// 		if (aes_send_vld_1t3)
	// 			begin
	// 				`AES_SEND({
	// 				aes_send_data_1,		// 32 bits of data
					
	// 				8'h00,		//   8 bits pad                            <--------32bit boundary
	// 				ds_aes_retire_zbits_1t3[3:0],		//  4 bits of zbit info
	// 				ds_aes_retire_dw_1t3,		//  1 bit of DW info
	// 				ds_aes_retire_type_1t3[2:0],		//  3 bits of type info
					
	// 				1'b0,		//  1 bit - no need to mask now
	// 				ds_aes_retire_rtag_1t3[6:0],		//  7 bits of rtag info
					
	// 				ds_aes_retire_atag_1t3[7:0],		//  8 bits of atag info
					

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 				clusterid,
	// 				2'b00,		//  2 bits pad
	// 				cpuid,		//  2 bits for cpuid
	// 				`T_AES,					//  4 bits type
	// 				cycle[31:0]		// 32 bit cycle count
	// 				});		// total   96 bits = 12 bytes
				
	// 		end
			
	// 		if (aes_send_vld_2t3)
	// 			begin
	// 				`AES_SEND({
	// 				aes_send_data_2,		// 32 bits of data
					
	// 				8'h00,		//   8 bits pad                            <--------32bit boundary
	// 				ds_aes_retire_zbits_2t3[3:0],		//  4 bits of zbit info
	// 				ds_aes_retire_dw_2t3,		//  1 bit of DW info
	// 				ds_aes_retire_type_2t3[2:0],		//  3 bits of type info
					
	// 				1'b0,		//  1 bit - no need to mask now
	// 				ds_aes_retire_rtag_2t3[6:0],		//  7 bits of rtag info
					
	// 				ds_aes_retire_atag_2t3[7:0],		//  8 bits of atag info
					

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 				clusterid,
	// 				2'b00,		//  2 bits pad
	// 				cpuid,		//  2 bits for cpuid
	// 				`T_AES,					//  4 bits type
	// 				cycle[31:0]		// 32 bit cycle count
	// 				});		// total   96 bits = 12 bytes
				
	// 		end
			
	// 		if (aes_send_vld_3t3)
	// 			begin
	// 				`AES_SEND({
	// 				aes_send_data_3,		// 32 bits of data
					
	// 				8'h00,		//   8 bits pad                            <--------32bit boundary
	// 				ds_aes_retire_zbits_3t3[3:0],		//  4 bits of zbit info
	// 				ds_aes_retire_dw_3t3,		//  1 bit of DW info
	// 				ds_aes_retire_type_3t3[2:0],		//  3 bits of type info
					
	// 				1'b0,		//  1 bit - no need to mask now
	// 				ds_aes_retire_rtag_3t3[6:0],		//  7 bits of rtag info
					
	// 				ds_aes_retire_atag_3t3[7:0],		//  8 bits of atag info
					

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 				clusterid,
	// 				2'b00,		//  2 bits pad
	// 				cpuid,		//  2 bits for cpuid
	// 				`T_AES,					//  4 bits type
	// 				cycle[31:0]		// 32 bit cycle count
	// 				});		// total   96 bits = 12 bytes
				
	// 		end
			
	// 		if (aes_send_vld_4t3)
	// 			begin
	// 				`AES_SEND({
	// 				aes_send_data_4,		// 32 bits of data
					
	// 				8'h00,		//   8 bits pad                            <--------32bit boundary
	// 				ds_aes_retire_zbits_4t3[3:0],		//  4 bits of zbit info
	// 				ds_aes_retire_dw_4t3,		//  1 bit of DW info
	// 				ds_aes_retire_type_4t3[2:0],		//  3 bits of type info
					
	// 				1'b0,		//  1 bit - no need to mask now
	// 				ds_aes_retire_rtag_4t3[6:0],		//  7 bits of rtag info
					
	// 				ds_aes_retire_atag_4t3[7:0],		//  8 bits of atag info
					

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 				clusterid,
	// 				2'b00,		//  2 bits pad
	// 				cpuid,		//  2 bits for cpuid
	// 				`T_AES,					//  4 bits type
	// 				cycle[31:0]		// 32 bit cycle count
	// 				});		// total   96 bits = 12 bytes
				
	// 		end
			
	// 		if (aes_send_vld_5t3)
	// 			begin
	// 				`AES_SEND({
	// 				aes_send_data_5,		// 32 bits of data
					
	// 				8'h00,		//   8 bits pad                            <--------32bit boundary
	// 				ds_aes_retire_zbits_5t3[3:0],		//  4 bits of zbit info
	// 				ds_aes_retire_dw_5t3,		//  1 bit of DW info
	// 				ds_aes_retire_type_5t3[2:0],		//  3 bits of type info
					
	// 				1'b0,		//  1 bit - no need to mask now
	// 				ds_aes_retire_rtag_5t3[6:0],		//  7 bits of rtag info
					
	// 				ds_aes_retire_atag_5t3[7:0],		//  8 bits of atag info
					

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 				clusterid,
	// 				2'b00,		//  2 bits pad
	// 				cpuid,		//  2 bits for cpuid
	// 				`T_AES,					//  4 bits type
	// 				cycle[31:0]		// 32 bit cycle count
	// 				});		// total   96 bits = 12 bytes
				
	// 		end
	// 		////---------------------- Revised by sbc@2014-04-10 11:57 BEGIN----------------------

	// 		`ifdef RAVEN_COSIM
	// 		if (aes_send_vld_0t3) begin
	// 			if(cpuid==0) begin
	// 				aes_buff0={
	// 					aes_send_data_0,		// 32 bits of data
						
	// 					8'h00,		//   8 bits pad                            <--------32bit boundary
	// 					ds_aes_retire_zbits_0t3[3:0],		//  4 bits of zbit info
	// 					ds_aes_retire_dw_0t3,		//  1 bit of DW info
	// 					ds_aes_retire_type_0t3[2:0],		//  3 bits of type info
						
	// 					1'b0,		//  1 bit - no need to mask now
	// 					ds_aes_retire_rtag_0t3[6:0],		//  7 bits of rtag info
						
	// 					ds_aes_retire_atag_0t3[7:0],		//  8 bits of atag info
						

	// 					`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 					64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 					`else

	// 					32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 					`endif//}

	// 					16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_AES,					//  4 bits type
						
	// 					cycle[31:0]		// 32 bit cycle count
	// 					};
	// 				if(raven_cosim_debug)
	// 					$display("%t, atag %x:%x:%x", $time, ds_aes_retire_atag_0t3[7:0], aes_send_data_0, ds_aes_retire_type_0t3[2:0]);
	// 				//aes_flag0=verify_register(aes_buff0);
	// 				aes_mem[aes_mem_ptr]=aes_buff0[511:0];
	// 				aes_mem_ptr=aes_mem_ptr+1;
	// 				if(aes_mem_ptr=={`AES_MEM_PTR_SIZE{1'b0}})
	// 					aes_flag0=verify_register(aes_mem_ptr);
	// 				if(aes_flag0==2) begin
	// 					$display("COSIM_ERROR: REG CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag0==1) begin
	// 					$display("COSIM_ERROR: INSTRUCTION CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag0==3) begin
	// 					$display("COSIM_ERROR: MEM CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag0==5) begin
	// 					$display("COSIM_WARNING: INCOMPLETE CHECK!");
	// 				end
	// 			end
	// 		end
	// 		if (aes_send_vld_1t3) begin
	// 			if(cpuid==0) begin
	// 				aes_buff1={
	// 					aes_send_data_1,		// 32 bits of data
						
	// 					8'h00,		//   8 bits pad                            <--------32bit boundary
	// 					ds_aes_retire_zbits_1t3[3:0],		//  4 bits of zbit info
	// 					ds_aes_retire_dw_1t3,		//  1 bit of DW info
	// 					ds_aes_retire_type_1t3[2:0],		//  3 bits of type info
						
	// 					1'b0,		//  1 bit - no need to mask now
	// 					ds_aes_retire_rtag_1t3[6:0],		//  7 bits of rtag info
						
	// 					ds_aes_retire_atag_1t3[7:0],		//  8 bits of atag info
						

	// 					`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 					64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 					`else

	// 					32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 					`endif//}

	// 					16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_AES,					//  4 bits type
						
	// 					cycle[31:0]		// 32 bit cycle count
	// 					};
	// 				if(raven_cosim_debug)
	// 					$display("%t, atag %x:%x:%x", $time, ds_aes_retire_atag_1t3[7:0], aes_send_data_1, ds_aes_retire_type_1t3[2:0]);
	// 				//aes_flag1=verify_register(aes_buff1);
	// 				aes_mem[aes_mem_ptr]=aes_buff1[511:0];
	// 				aes_mem_ptr=aes_mem_ptr+1;
	// 				if(aes_mem_ptr=={`AES_MEM_PTR_SIZE{1'b0}})
	// 					aes_flag1=verify_register(aes_mem_ptr);
	// 				if(aes_flag1==2) begin
	// 					$display("COSIM_ERROR: REG CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag1==1) begin
	// 					$display("COSIM_ERROR: INSTRUCTION CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag1==3) begin
	// 					$display("COSIM_ERROR: MEM CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag1==5) begin
	// 					$display("COSIM_WARNING: INCOMPLETE CHECK!");
	// 				end
	// 			end
	// 		end
	// 		if (aes_send_vld_2t3) begin
	// 			if(cpuid==0) begin
	// 				aes_buff2={
	// 					aes_send_data_2,		// 32 bits of data
						
	// 					8'h00,		//   8 bits pad                            <--------32bit boundary
	// 					ds_aes_retire_zbits_2t3[3:0],		//  4 bits of zbit info
	// 					ds_aes_retire_dw_2t3,		//  1 bit of DW info
	// 					ds_aes_retire_type_2t3[2:0],		//  3 bits of type info
						
	// 					1'b0,		//  1 bit - no need to mask now
	// 					ds_aes_retire_rtag_2t3[6:0],		//  7 bits of rtag info
						
	// 					ds_aes_retire_atag_2t3[7:0],		//  8 bits of atag info
						

	// 					`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 					64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 					`else

	// 					32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 					`endif//}

	// 					16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_AES,					//  4 bits type
						
	// 					cycle[31:0]		// 32 bit cycle count
	// 					};
	// 				if(raven_cosim_debug)
	// 					$display("%t, atag %x:%x:%x", $time, ds_aes_retire_atag_2t3[7:0], aes_send_data_2, ds_aes_retire_type_2t3[2:0]);
	// 				//aes_flag2=verify_register(aes_buff2);
	// 				aes_mem[aes_mem_ptr]=aes_buff2[511:0];
	// 				aes_mem_ptr=aes_mem_ptr+1;
	// 				if(aes_mem_ptr=={`AES_MEM_PTR_SIZE{1'b0}})
	// 					aes_flag2=verify_register(aes_mem_ptr);
	// 				if(aes_flag2==2) begin
	// 					$display("COSIM_ERROR: REG CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag2==1) begin
	// 					$display("COSIM_ERROR: INSTRUCTION CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag2==3) begin
	// 					$display("COSIM_ERROR: MEM CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag2==5) begin
	// 					$display("COSIM_WARNING: INCOMPLETE CHECK!");
	// 				end
	// 			end
	// 		end
	// 		if (aes_send_vld_3t3) begin
	// 			if(cpuid==0) begin
	// 				aes_buff3={
	// 					aes_send_data_3,		// 32 bits of data
						
	// 					8'h00,		//   8 bits pad                            <--------32bit boundary
	// 					ds_aes_retire_zbits_3t3[3:0],		//  4 bits of zbit info
	// 					ds_aes_retire_dw_3t3,		//  1 bit of DW info
	// 					ds_aes_retire_type_3t3[2:0],		//  3 bits of type info
						
	// 					1'b0,		//  1 bit - no need to mask now
	// 					ds_aes_retire_rtag_3t3[6:0],		//  7 bits of rtag info
						
	// 					ds_aes_retire_atag_3t3[7:0],		//  8 bits of atag info
						

	// 					`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 					64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 					`else

	// 					32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 					`endif//}

	// 					16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_AES,					//  4 bits type
						
	// 					cycle[31:0]		// 32 bit cycle count
	// 					};
	// 				if(raven_cosim_debug)
	// 					$display("%t, atag %x:%x:%x", $time, ds_aes_retire_atag_3t3[7:0], aes_send_data_3, ds_aes_retire_type_3t3[2:0]);
	// 				//aes_flag3=verify_register(aes_buff3);
	// 				aes_mem[aes_mem_ptr]=aes_buff3[511:0];
	// 				aes_mem_ptr=aes_mem_ptr+1;
	// 				if(aes_mem_ptr=={`AES_MEM_PTR_SIZE{1'b0}})
	// 					aes_flag3=verify_register(aes_mem_ptr);
	// 				if(aes_flag3==2) begin
	// 					$display("COSIM_ERROR: REG CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag3==1) begin
	// 					$display("COSIM_ERROR: INSTRUCTION CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag3==3) begin
	// 					$display("COSIM_ERROR: MEM CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag3==5) begin
	// 					$display("COSIM_WARNING: INCOMPLETE CHECK!");
	// 				end
	// 			end
	// 		end
	// 		if (aes_send_vld_4t3) begin
	// 			if(cpuid==0) begin
	// 				aes_buff4={
	// 					aes_send_data_4,		// 32 bits of data
						
	// 					8'h00,		//   8 bits pad                            <--------32bit boundary
	// 					ds_aes_retire_zbits_4t3[3:0],		//  4 bits of zbit info
	// 					ds_aes_retire_dw_4t3,		//  1 bit of DW info
	// 					ds_aes_retire_type_4t3[2:0],		//  3 bits of type info
						
	// 					1'b0,		//  1 bit - no need to mask now
	// 					ds_aes_retire_rtag_4t3[6:0],		//  7 bits of rtag info
						
	// 					ds_aes_retire_atag_4t3[7:0],		//  8 bits of atag info
						

	// 					`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 					64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 					`else

	// 					32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 					`endif//}

	// 					16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_AES,					//  4 bits type
						
	// 					cycle[31:0]		// 32 bit cycle count
	// 					};
	// 				if(raven_cosim_debug)
	// 					$display("%t, atag %x:%x:%x", $time, ds_aes_retire_atag_4t3[7:0], aes_send_data_4, ds_aes_retire_type_4t3[2:0]);
	// 				//aes_flag4=verify_register(aes_buff4);
	// 				aes_mem[aes_mem_ptr]=aes_buff4[511:0];
	// 				aes_mem_ptr=aes_mem_ptr+1;
	// 				if(aes_mem_ptr=={`AES_MEM_PTR_SIZE{1'b0}})
	// 					aes_flag4=verify_register(aes_mem_ptr);
	// 				if(aes_flag4==2) begin
	// 					$display("COSIM_ERROR: REG CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag4==1) begin
	// 					$display("COSIM_ERROR: INSTRUCTION CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag4==3) begin
	// 					$display("COSIM_ERROR: MEM CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag4==5) begin
	// 					$display("COSIM_WARNING: INCOMPLETE CHECK!");
	// 				end
	// 			end
	// 		end
	// 		if (aes_send_vld_5t3) begin
	// 			if(cpuid==0) begin
	// 				aes_buff5={
	// 					aes_send_data_5,		// 32 bits of data
						
	// 					8'h00,		//   8 bits pad                            <--------32bit boundary
	// 					ds_aes_retire_zbits_5t3[3:0],		//  4 bits of zbit info
	// 					ds_aes_retire_dw_5t3,		//  1 bit of DW info
	// 					ds_aes_retire_type_5t3[2:0],		//  3 bits of type info
						
	// 					1'b0,		//  1 bit - no need to mask now
	// 					ds_aes_retire_rtag_5t3[6:0],		//  7 bits of rtag info
						
	// 					ds_aes_retire_atag_5t3[7:0],		//  8 bits of atag info
						

	// 					`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 					64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 					`else

	// 					32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 					`endif//}

	// 					16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_AES,					//  4 bits type
						
	// 					cycle[31:0]		// 32 bit cycle count
	// 					};
	// 				if(raven_cosim_debug)
	// 					$display("%t, atag %x:%x:%x", $time, ds_aes_retire_atag_5t3[7:0], aes_send_data_5, ds_aes_retire_type_5t3[2:0]);
	// 				//aes_flag5=verify_register(aes_buff5);
	// 				aes_mem[aes_mem_ptr]=aes_buff5[511:0];
	// 				aes_mem_ptr=aes_mem_ptr+1;
	// 				if(aes_mem_ptr=={`AES_MEM_PTR_SIZE{1'b0}})
	// 					aes_flag5=verify_register(aes_mem_ptr);
	// 				if(aes_flag5==2) begin
	// 					$display("COSIM_ERROR: REG CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag5==1) begin
	// 					$display("COSIM_ERROR: INSTRUCTION CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag5==3) begin
	// 					$display("COSIM_ERROR: MEM CHECK ERROR!");
	// 					$finish;
	// 				end
	// 				else if(aes_flag5==5) begin
	// 					$display("COSIM_WARNING: INCOMPLETE CHECK!");
	// 				end
	// 			end
	// 		end
	// 		`endif // RAVEN_COSIM

	// 		////---------------------- Revised by sbc@2014-04-10 11:57 END------------------------
			
	// 		//Those 4 packets are intermmediate results for the Fused Parent(AESE/AESD)
	// 		if (crypto_aes_vld_t3_q)
	// 			begin
	// 				`AES_SEND({
	// 				crypto_aes_out_t3_q[31:0],		// 32 bits of data
	// 				1'b0,
	// 				crypto_aes_gid_t3_q,		//  8 bits pad(overload to have fusion gid)<--------32bit boundary
	// 				4'b0000,		//  4 bits of zbit info
	// 				1'b1,		//  1 bit of DW info
	// 				3'b110,		//  3 bits of type info(3'b110 is not used in RTL)
	// 				1'b0,		//  1 bit - no need to mask now
	// 				crypto_rtag_t3_q,		//  7 bits of rtag info
	// 				8'h0,		//  8 bits of atag info(Fill in index[4:0] later in TnC_CPU)

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 				clusterid,
	// 				2'b00,		//  2 bits pad
	// 				cpuid,		//  2 bits for cpuid
	// 				`T_AES,					//  4 bits type
	// 				cycle[31:0]		// 32 bit cycle count
	// 				});		// total   96 bits = 12 bytes
	// 			`AES_SEND({
	// 			crypto_aes_out_t3_q[63:32],		// 32 bits of data
	// 				1'b0,
	// 				crypto_aes_gid_t3_q,		//  8 bits pad(overload to have fusion gid)<--------32bit boundary
	// 				4'b0000,		//  4 bits of zbit info
	// 				1'b1,		//  1 bit of DW info
	// 				3'b110,		//  3 bits of type info(3'b110 is not used in RTL)
	// 				1'b0,		//  1 bit - no need to mask now
	// 				crypto_rtag_t3_q,		//  7 bits of rtag info
	// 				8'h40,		//  8 bits of atag info(Fill in index[4:0] later in TnC_CPU)

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 				clusterid,
	// 				2'b00,		//  2 bits pad
	// 				cpuid,		//  2 bits for cpuid
	// 				`T_AES,					//  4 bits type
	// 				cycle[31:0]		// 32 bit cycle count
	// 				});		// total   96 bits = 12 bytes
	// 			`AES_SEND({
	// 			crypto_aes_out_t3_q[95:64],		// 32 bits of data
	// 				1'b0,
	// 				crypto_aes_gid_t3_q,		//  8 bits pad(overload to have fusion gid)<--------32bit boundary
	// 				4'b0000,		//  4 bits of zbit info
	// 				1'b1,		//  1 bit of DW info
	// 				3'b110,		//  3 bits of type info(3'b110 is not used in RTL)
	// 				1'b0,		//  1 bit - no need to mask now
	// 				crypto_rtag_t3_q,		//  7 bits of rtag info
	// 				8'h80,		//  8 bits of atag info(Fill in index[4:0] later in TnC_CPU)

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 				clusterid,
	// 				2'b00,		//  2 bits pad
	// 				cpuid,		//  2 bits for cpuid
	// 				`T_AES,					//  4 bits type
	// 				cycle[31:0]		// 32 bit cycle count
	// 				});		// total   96 bits = 12 bytes
	// 			`AES_SEND({
	// 			crypto_aes_out_t3_q[127:96],		// 32 bits of data
	// 				1'b0,
	// 				crypto_aes_gid_t3_q,		//  8 bits pad(overload to have fusion gid)<--------32bit boundary
	// 				4'b0000,		//  4 bits of zbit info
	// 				1'b1,		//  1 bit of DW info
	// 				3'b110,		//  3 bits of type info(3'b110 is not used in RTL)
	// 				1'b0,		//  1 bit - no need to mask now
	// 				crypto_rtag_t3_q,		//  7 bits of rtag info
	// 				8'hc0,		//  8 bits of atag info(Fill in index[4:0] later in TnC_CPU)

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 				clusterid,
	// 				2'b00,		//  2 bits pad
	// 				cpuid,		//  2 bits for cpuid
	// 				`T_AES,					//  4 bits type
	// 				cycle[31:0]		// 32 bit cycle count
	// 				});		// total   96 bits = 12 bytes
	// 		end
	// 	end
	// end
	
	///////////////////////////////////////////////////////////////////////
	// Pipe uop iface out to p2
	///////////////////////////////////////////////////////////////////////
	
	reg [63:0]	ia_0p2_q;
	reg [63:0]	ia_1p2_q;
	reg [63:0]	ia_2p2_q;
	////---------------------- Revised by sbc@2014-03-12 10:32----------------------------
	reg [63:0]	ia_3p2_q;
	
	always @ (posedge ck_gclkcr)
		begin
			if ( reset )
			begin
				ia_0p2_q <= `PRJ_DFF_DELAY 1'b0;
			ia_1p2_q <= `PRJ_DFF_DELAY 1'b0;
			ia_2p2_q <= `PRJ_DFF_DELAY 1'b0;
			////---------------------- Revised by sbc@2014-03-12 10:38----------------------------
			ia_3p2_q <= `XM_DFF_DELAY 1'b0;
		end
		else
			begin
				ia_0p2_q <= `PRJ_DFF_DELAY {(ia_0p1[63:32] & {32{dsu_aarch64_state}}),ia_0p1[31:0]};
			ia_1p2_q <= `PRJ_DFF_DELAY {(ia_1p1[63:32] & {32{dsu_aarch64_state}}),ia_1p1[31:0]};
			ia_2p2_q <= `PRJ_DFF_DELAY {(ia_2p1[63:32] & {32{dsu_aarch64_state}}),ia_2p1[31:0]};
			////---------------------- Revised by sbc@2014-03-12 10:38----------------------------
			ia_3p2_q <= `XM_DFF_DELAY {(ia_3p1[63:32] & {32{dsu_aarch64_state}}),ia_3p1[31:0]};
		end
	end
	
	///////////////////////////////////////////////////////////////////////
	// Pipe uop Gid out to p3
	///////////////////////////////////////////////////////////////////////
	
	reg [6:0]       gid_0p3;
	reg [6:0]       gid_1p3;
	reg [6:0]       gid_2p3;
	////---------------------- Revised by sbc@2014-03-12 10:38----------------------------
	reg [6:0]       gid_3p3;
	
	always @ (posedge ck_gclkcr)
		begin
			if ( reset )
			begin
				gid_0p3 <= `PRJ_DFF_DELAY 6'b0;
			gid_1p3 <= `PRJ_DFF_DELAY 6'b0;
			gid_2p3 <= `PRJ_DFF_DELAY 6'b0;
			////---------------------- Revised by sbc@2014-03-12 10:39----------------------------
			gid_3p3 <= `XM_DFF_DELAY 6'b0;
		end
		else
			begin
				gid_0p3 <= `PRJ_DFF_DELAY gid_0p2_q;
			gid_1p3 <= `PRJ_DFF_DELAY gid_1p2_q;
			gid_2p3 <= `PRJ_DFF_DELAY gid_2p2_q;
			////---------------------- Revised by sbc@2014-03-12 10:39----------------------------
			gid_3p3 <= `XM_DFF_DELAY gid_3p2_q;
		end
	end
	
	
	///////////////////////////////////////////////////////////////////////
	// Pipe flush signals out to u6
	///////////////////////////////////////////////////////////////////////
	
	always @ (posedge ck_gclkcr)
		begin
			if ( reset )
			begin
				ds_debug_start_u2     <= `PRJ_DFF_DELAY 1'b0;
			ds_flush_u2           <= `PRJ_DFF_DELAY 1'b0;
			dsu_flush_u1           <= `PRJ_DFF_DELAY 1'b0;
			ds_flush_trgt_aarch64_u1           <= `PRJ_DFF_DELAY 1'b0;
			ds_flush_trgt_aarch64_u2           <= `PRJ_DFF_DELAY 1'b0;
			bx_flush_u2           <= `PRJ_DFF_DELAY 1'b0;
			bru_flush_u1           <= `PRJ_DFF_DELAY 1'b0;
			flush_u1              <= `PRJ_DFF_DELAY 1'b0;
			flush_u2              <= `PRJ_DFF_DELAY 1'b0;
			flush_u3              <= `PRJ_DFF_DELAY 1'b0;
			flush_u4              <= `PRJ_DFF_DELAY 1'b0;
			flush_u5              <= `PRJ_DFF_DELAY 1'b0;
			flush_u6              <= `PRJ_DFF_DELAY 1'b0;
		end
		else
			begin
				flush_u1 <= `PRJ_DFF_DELAY bru_flush | dsu_flush;
			flush_u2 <= `PRJ_DFF_DELAY flush_u1;
			flush_u3 <= `PRJ_DFF_DELAY bx_flush_u2 | ds_flush_u2;
			flush_u4 <= `PRJ_DFF_DELAY flush_u3;
			flush_u5 <= `PRJ_DFF_DELAY flush_u4;
			flush_u6 <= `PRJ_DFF_DELAY flush_u5;
			flush_gid_u1 <= `PRJ_DFF_DELAY dsu_flush ? dsu_flush_gid : bru_flush_gid;
			flush_gid_u2 <= `PRJ_DFF_DELAY flush_gid_u1;
			flush_gid_u3 <= `PRJ_DFF_DELAY ds_flush_u2 ? ds_flush_gid_u2 : bx_flush_gid_u2;
			flush_gid_u4 <= `PRJ_DFF_DELAY flush_gid_u3;
			flush_gid_u5 <= `PRJ_DFF_DELAY flush_gid_u4;
			flush_gid_u6 <= `PRJ_DFF_DELAY flush_gid_u5;
			
			
			ds_debug_start_u2     <= `XM_DFF_DELAY debug_start;
			ds_flush_u2           <= `XM_DFF_DELAY dsu_flush_u1;
			dsu_flush_u1           <= `XM_DFF_DELAY dsu_flush;
			ds_flush_trgt_aarch64_u1           <= `XM_DFF_DELAY dsu_flush_trgt_aarch64;
			ds_flush_trgt_aarch64_u2           <= `XM_DFF_DELAY ds_flush_trgt_aarch64_u1;
			ds_flush_gid_u2[6:0]  <= `XM_DFF_DELAY ds_flush_gid_u1[6:0];
			ds_flush_gid_u1[6:0]  <= `XM_DFF_DELAY dsu_flush_gid[6:0];
			ds_flush_type_u2[5:0] <= `XM_DFF_DELAY ds_flush_type_u1[5:0];
			ds_flush_type_u1[5:0] <= `XM_DFF_DELAY dsu_flush_type[5:0];
			bx_flush_u2           <= `XM_DFF_DELAY bru_flush_u1;
			bru_flush_u1           <= `XM_DFF_DELAY bru_flush;
			bx_flush_gid_u2[6:0]  <= `XM_DFF_DELAY bru_flush_gid_u1[6:0];
			bru_flush_gid_u1[6:0]  <= `XM_DFF_DELAY bru_flush_gid[6:0];
			stg2_exc_u0           <= `XM_DFF_DELAY stg2_exc_x1;
			stg2_exc_u1           <= `XM_DFF_DELAY stg2_exc_u0;
			stg2_exc_u2           <= `XM_DFF_DELAY stg2_exc_u1;
			
			algn_exc_u0           <= `XM_DFF_DELAY algn_exc_x1;
			algn_exc_u1           <= `XM_DFF_DELAY algn_exc_u0;
			algn_exc_u2           <= `XM_DFF_DELAY algn_exc_u1;
			
			sp_algn_exc_u0           <= `XM_DFF_DELAY sp_algn_exc_x1;
			sp_algn_exc_u1           <= `XM_DFF_DELAY sp_algn_exc_u0;
			sp_algn_exc_u2           <= `XM_DFF_DELAY sp_algn_exc_u1;
		end
	end
	
	///////////////////////////////////////////////////////////////////////
	// opcodes and uops.  handle all the speculativeness in verilog
	// // to avoid complexity on the c side
	// load result data also grabbed here
	///////////////////////////////////////////////////////////////////////
	
	`define OPC_FIFO_WIDTH       38
	`define OPC_FIFO_ALL         37:0
	`define OPC_FIFO_FUSEDPARENT 37
	`define OPC_FIFO_IFU_PCALGN_ABT_PEND 36
	`define OPC_FIFO_LB_END      35
	`define OPC_FIFO_LB_START    34
	`define OPC_FIFO_ISIZE       33
	`define OPC_FIFO_TBIT        32
	`define OPC_FIFO_OPCODE      31:0
	
	parameter OPC_FIFO_SIZE=64;
	reg fusion_opc_fifo[OPC_FIFO_SIZE];
	reg [5:0]  fusion_opc_fifo_rd_ptr;
	reg [5:0]  fusion_opc_fifo_wr_ptr;
	reg [`OPC_FIFO_ALL] opc_fifo[OPC_FIFO_SIZE];
	reg [5:0]  opc_fifo_rd_ptr;
	reg [5:0]  opc_fifo_wr_ptr;
	
	// opcode in p2 for core testbench
	wire[31:0] opcode0_nxt;
	wire[31:0] opcode1_nxt;
	wire[31:0] opcode2_nxt;
	reg [31:0] opcode_0p2;
	reg [31:0] opcode_1p2;
	reg [31:0] opcode_2p2;
	////---------------------- Revised by sbc@2014-03-12 10:40 BEGIN----------------------
	wire[31:0] opcode3_nxt;
	reg [31:0] opcode_3p2;
	////---------------------- Revised by sbc@2014-03-12 10:40 END------------------------
	
	wire[5:0]  opc_fifo_rd_ptr_plus1;
	wire[5:0]  opc_fifo_rd_ptr_plus2;
	assign opc_fifo_rd_ptr_plus1[5:0] = opc_fifo_rd_ptr[5:0] + 6'b000001;
	assign opc_fifo_rd_ptr_plus2[5:0] = opc_fifo_rd_ptr[5:0] + 6'b000010;
	
	assign opcode0_nxt = uop_vld_0p2_q ? opc_fifo[opc_fifo_rd_ptr] : 32'hx;
	assign opcode1_nxt = uop_vld_1p2_q ? (inst_end_0p2_q ? opc_fifo[opc_fifo_rd_ptr_plus1] : opc_fifo[opc_fifo_rd_ptr]) : 32'hx;
	assign opcode2_nxt = uop_vld_2p2_q ? ((inst_end_0p2_q && inst_end_1p2_q) ? opc_fifo[opc_fifo_rd_ptr_plus2] :
		(inst_end_0p2_q || inst_end_1p2_q) ? opc_fifo[opc_fifo_rd_ptr_plus1] :
		opc_fifo[opc_fifo_rd_ptr]) : 32'hx;
	////---------------------- Revised by sbc@2014-03-12 10:54 BEGIN----------------------
	wire[5:0]  opc_fifo_rd_ptr_plus3;
	assign opc_fifo_rd_ptr_plus3[5:0] = opc_fifo_rd_ptr[5:0] + 6'b000011;
	
	assign opcode3_nxt = uop_vld_3p2_q ? ((inst_end_0p2_q && inst_end_1p2_q && inst_end_2p2_q) ? opc_fifo[opc_fifo_rd_ptr_plus3] :
		(inst_end_0p2_q && inst_end_1p2_q) ? opc_fifo[opc_fifo_rd_ptr_plus2] :
		(inst_end_0p2_q && inst_end_2p2_q) ? opc_fifo[opc_fifo_rd_ptr_plus2] :
		(inst_end_1p2_q && inst_end_2p2_q) ? opc_fifo[opc_fifo_rd_ptr_plus2] :
		(inst_end_0p2_q || inst_end_1p2_q || inst_end_2p2_q) ? opc_fifo[opc_fifo_rd_ptr_plus1] :
		opc_fifo[opc_fifo_rd_ptr]) : 32'hx;
	
	always @(negedge ck_gclkcr) begin
		if (reset) begin
			{opcode_0p2,opcode_1p2,opcode_2p2,opcode_3p2} <= `XM_DFF_DELAY 96'hx;
		end else begin
			{opcode_0p2,opcode_1p2,opcode_2p2,opcode_3p2} <= `XM_DFF_DELAY {opcode0_nxt,opcode1_nxt,opcode2_nxt,opcode3_nxt};
		end
	end
	////---------------------- Revised by sbc@2014-03-12 10:56 END------------------------
	
	reg  in_preamble;		// state bit - 1 when ID is issuing a preamble - set by dsu_prestart, cleared by pre_end_Xp2_q
	reg  skip_preamble;		// state bit - 1 when ID is issuing a preamble after a SLNT_BRN(chicken bit controlled) - set by ds_flush_u2, cleared by dsu_ia_restart
	
	`define INST_FIFO_ALL        194:0	// one complete inst_fifo entry
	`define INST_FIFO_GID_SPLIT  194        // DW producer and SW consume forced gid split
	`define INST_FIFO_FUSED_RTAG 193:187    // 7 bit rtag info for the Fused Parent: This is to re-order the AES pkt
	`define INST_FIFO_FUSEDPARENT 186   // indicate if a instruction is the parent of a pair of fused instructions
	`define INST_FIFO_WFEWFI_HLT 185        // indicate if a WFE or WFI is active without a pending event/interrupt. This means core will enter halt
	`define INST_FIFO_SP_ALGN_EXC   184
	`define INST_FIFO_ALGN_EXC   183
	`define INST_FIFO_STG2_EXC   182
	`define INST_FIFO_PWR_CYC    181
	`define INST_FIFO_OPC_VLD    180
	`define INST_FIFO_GRPIDXING  179
	`define INST_FIFO_IFU_PCALGN_ABT_PEND     178
	`define INST_FIFO_LB_END     177
	`define INST_FIFO_LB_START   176
	`define INST_FIFO_LB_VALID   175
	`define INST_FIFO_STREX      174	// 1 bit indicating strex
	`define INST_FIFO_ITBITS     173:166    // itbits just before this instruction
	`define INST_FIFO_GID_WRAP   165	// the gid wrap bit
	`define INST_FIFO_GID        164:159	// the 6 bit gid (without wrap bit)
	`define INST_FIFO_GID_FULL   165:159	// the full 7-bit gid
	`define INST_FIFO_EXC_FULL   158:151
	`define INST_FIFO_EXC_TYP    158:152
	`define INST_FIFO_EXC_EN     151
	`define INST_FIFO_SPW_CNT    150:143	// 8 bits, the number of spw results expected
	`define INST_FIFO_AES_CNT    142:135	// 8 bits, the number of aes results expected
	`define INST_FIFO_PSR_CNT    134:127	// 8 bits, the number of psr results expected
	`define INST_FIFO_NMOP       126:123	// 4 bits, total Number of Memory Ops:Max is 15 from LDM/STM
	`define INST_FIFO_MSIZE      122:120	// 3 bits, total memory size in bytes of this uop
	`define INST_FIFO_ESIZE      119:117	// 3 bits, ld/st element size in bytes
	`define INST_FIFO_ST_BYTES   116:109	// 8 bits, the number of str bytes expected
	`define INST_FIFO_LD_BYTES   108:101	// 8 bits, the number of lod bytes expected
	`define INST_FIFO_ISIZE      100 	// 32 bit opcode, one bit tbit, one bit size
	`define INST_FIFO_TBIT       99 	// 32 bit opcode, one bit tbit, one bit size
	`define INST_FIFO_OPCODE     98:67     // 32 bit opcode, one bit tbit, one bit size
	`define INST_FIFO_OPCODE_HW2 98:83     // opcode hw2 - needed for opcode coverage
	`define INST_FIFO_OPCODE_HW1 82:67     // opcode hw1 - needed for opcode coverage
	`define INST_FIFO_IA         66:3      // 63-bit inst addr
	`define INST_FIFO_COMMITTED  2		// one bit status
	`define INST_FIFO_COMPLETE   1		// one bit status
	`define INST_FIFO_VLD        0		// one bit status
	
	`define LOAD_FIFO_WIDTH      380
	`define LOAD_FIFO_ALL        379:0
	`define LOAD_FIFO_VA_VLD     379        // 1 bit va valid bit(core tb mostly)
	`define LOAD_FIFO_2ND_PA     378:334    // 45 bit PA
	`define LOAD_FIFO_2ND_ATTR   333:321    // 13 bit attr
	`define LOAD_FIFO_UNALIGNED  320        // 1 bit, ccfail flag
	`define LOAD_FIFO_CCFAIL     319        // 1 bit, ccfail flag
	`define LOAD_FIFO_SEXT       318        // 1 bit, load SExt bit
	`define LOAD_FIFO_DW         317        // 1 bit, DW bit
	`define LOAD_FIFO_INSTR      316:308    // 9 bits, entry in inst_fifo
	`define LOAD_FIFO_GID_WRAP   307        // 1 bit, gid wrap
	`define LOAD_FIFO_GID        306:301    // 6 bits, gid w/o wrap bit
	`define LOAD_FIFO_GID_FULL   307:301    // 7 bits, gid (may not need)
	`define LOAD_FIFO_ATTR       300:288    // 13 bits, page attr
	`define LOAD_FIFO_RESY_DATA  287:224    // 64 bits, dsty data
	`define LOAD_FIFO_DSTY_DVLD  223        // 1 bit tag valid
	`define LOAD_FIFO_DSTY_VLD   222        // 1 bit tag valid
	`define LOAD_FIFO_DSTY_RTAG  221:215    // 7 bits tag of dsty
	`define LOAD_FIFO_DSTY_ATAG  214:207    // 8 bits tag of dsty
	`define LOAD_FIFO_DSTY_TYPE  206:204    // 3 bits type of dsty
	`define LOAD_FIFO_RESX_DATA  203:140    // 64 bits, dstx data
	`define LOAD_FIFO_DSTX_DVLD  139        // 1 bit, tag valid
	`define LOAD_FIFO_DSTX_VLD   138        // 1 bit, tag valid
	`define LOAD_FIFO_DSTX_RTAG  137:131    // 7 bits, tag of dstx
	`define LOAD_FIFO_DSTX_ATAG  130:123    // 8 bits, tag of dstx
	`define LOAD_FIFO_DSTX_TYPE  122:120    // 3 bits, type of dstx
	`define LOAD_FIFO_PA         119:75     // 45 bits, PA of load
	`define LOAD_FIFO_VA         74:11      // 64 bits, VA of load
	`define LOAD_FIFO_LD_SIZE    10:3       // 8 bits, size of load (bytes)
	`define LOAD_FIFO_COMMITTED  2          // 1 bit, instr group was committed
	`define LOAD_FIFO_HAVE_ATTR  1          // 1 bit, got VA,PA,attr
	`define LOAD_FIFO_VLD        0          // 1 bit, entry valid
	
	parameter INST_FIFO_SIZE=512;
	reg [`INST_FIFO_ALL] inst_fifo[INST_FIFO_SIZE];
	reg [`INST_FIFO_ALL] inst_fifo_flushed;
	reg [`LOAD_FIFO_ALL] load_fifo[INST_FIFO_SIZE];
	reg [1:0] load_fifo_e[INST_FIFO_SIZE];
	
	//Imprecise Data Abort: Capture PA to make a list of NOISSCOMPARE lists
	`define IMP_DABT_FIFO_WIDTH      46
	`define IMP_DABT_FIFO_ALL        45:0
	`define IMP_DABT_FIFO_PA         45:1    // 45 bit PA
	`define IMP_DABT_FIFO_VLD        0       // 1 bit valid bit
	
	input l2_cpu_dext_err_r2;
	input l2_cpu_dvalid_r1;
	reg   l2_cpu_dvalid_r2;
	input [2:0] l2_cpu_dbufid_r1;
	reg   [2:0] l2_cpu_dbufid_r2;
	input [44:0] fb0_pa;
	input [44:0] fb1_pa;
	input [44:0] fb2_pa;
	input [44:0] fb3_pa;
	input [44:0] fb4_pa;
	input [44:0] fb5_pa;
	reg [`IMP_DABT_FIFO_ALL] imp_data_abort0;
	reg [`IMP_DABT_FIFO_ALL] imp_data_abort1;
	reg [`IMP_DABT_FIFO_ALL] imp_data_abort2;
	reg [`IMP_DABT_FIFO_ALL] imp_data_abort3;
	reg [`IMP_DABT_FIFO_ALL] imp_data_abort4;
	reg [`IMP_DABT_FIFO_ALL] imp_data_abort5;
	reg [`IMP_DABT_FIFO_ALL] imp_data_abort6;
	
	// always @(posedge ck_gclkcr) begin		//{
	// 	if (reset) begin		//{
	// 		imp_data_abort0 <= 46'b0;		//LS Fill Buffer0
	// 		imp_data_abort1 <= 46'b0;		//LS Fill Buffer1
	// 		imp_data_abort2 <= 46'b0;		//LS Fill Buffer2
	// 		imp_data_abort3 <= 46'b0;		//LS Fill Buffer3
	// 		imp_data_abort4 <= 46'b0;		//LS Fill Buffer4
	// 		imp_data_abort5 <= 46'b0;		//LS Fill Buffer5
	// 		imp_data_abort6 <= 46'b0;		//For L2 FEQ/ASQ
	// 		l2_cpu_dvalid_r2 <= 1'b0;
	// 		l2_cpu_dbufid_r2 <= 3'b0;
	// 	end		//}
	// 	else begin		//{
	// 		if(ds_exception_flush_u2 &
	// 			((ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PIMP_EXT_DABORT)|
	// 			(ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_VIMP_EXT_DABORT))) begin		//{
	// 				if(imp_data_abort0[0]) begin
	// 					`SEND_IMP_DABT({imp_data_abort0[45:1],

	// 					`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 					64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 					`else

	// 					32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 					`endif//}

	// 					16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_ABT,					//  4 bits type
	// 					cycle[31:0]		// 32 bit cycle count
	// 					});
	// 				imp_data_abort0 <= 46'b0;
	// 			end
	// 			if(imp_data_abort1[0])begin
	// 				`SEND_IMP_DABT({imp_data_abort1[45:1],

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_ABT,					//  4 bits type
	// 					cycle[31:0]		// 32 bit cycle count
	// 					});
	// 				imp_data_abort1 <= 46'b0;
	// 			end
	// 			if(imp_data_abort2[0])begin
	// 				`SEND_IMP_DABT({imp_data_abort2[45:1],

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_ABT,					//  4 bits type
	// 					cycle[31:0]		// 32 bit cycle count
	// 					});
	// 				imp_data_abort2 <= 46'b0;
	// 			end
	// 			if(imp_data_abort3[0])begin
	// 				`SEND_IMP_DABT({imp_data_abort3[45:1],

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_ABT,					//  4 bits type
	// 					cycle[31:0]		// 32 bit cycle count
	// 					});
	// 				imp_data_abort3 <= 46'b0;
	// 			end
	// 			if(imp_data_abort4[0])begin
	// 				`SEND_IMP_DABT({imp_data_abort4[45:1],

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_ABT,					//  4 bits type
	// 					cycle[31:0]		// 32 bit cycle count
	// 					});
	// 				imp_data_abort4 <= 46'b0;
	// 			end
	// 			if(imp_data_abort5[0])begin
	// 				`SEND_IMP_DABT({imp_data_abort5[45:1],

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_ABT,					//  4 bits type
	// 					cycle[31:0]		// 32 bit cycle count
	// 					});
	// 				imp_data_abort5 <= 46'b0;
	// 			end
	// 			if(imp_data_abort6[0])begin
	// 				`SEND_IMP_DABT({imp_data_abort6[45:1],

	// 				`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
	// 				64'h00000000,		//   64 bits pad                            <--------32bit boundary
	// 				`else

	// 				32'h00000000,		//   32 bits pad                            <--------32bit boundary
	// 				`endif//}

	// 				16'h0000,		//   16 bits pad                            <--------32bit boundary
	// 					clusterid,
	// 					2'b00,		//  2 bits pad
	// 					cpuid,		//  2 bits for cpuid
	// 					`T_ABT,					//  4 bits type
	// 					cycle[31:0]		// 32 bit cycle count
	// 					});
	// 				imp_data_abort6 <= 46'b0;
	// 			end
	// 		end		//}
	// 		if(l2_cpu_dvalid_r2 & l2_cpu_dext_err_r2) begin		//{
	// 			casez(l2_cpu_dbufid_r2[2:0])
	// 					3'b000: imp_data_abort0[`IMP_DABT_FIFO_ALL] <= {fb0_pa[44:0],1'b1};
	// 				3'b001: imp_data_abort1[`IMP_DABT_FIFO_ALL] <= {fb1_pa[44:0],1'b1};
	// 				3'b010: imp_data_abort2[`IMP_DABT_FIFO_ALL] <= {fb2_pa[44:0],1'b1};
	// 				3'b011: imp_data_abort3[`IMP_DABT_FIFO_ALL] <= {fb3_pa[44:0],1'b1};
	// 				3'b100: imp_data_abort4[`IMP_DABT_FIFO_ALL] <= {fb4_pa[44:0],1'b1};
	// 				3'b101: imp_data_abort5[`IMP_DABT_FIFO_ALL] <= {fb5_pa[44:0],1'b1};
	// 				default: ;
	// 			endcase
	// 		end		//}
	// 		//From L2(Skyros or ACE)
	// 		//Request Type     Skyros      ACE
	// 		//  *Read          FEQ         FEQ
	// 		//   Write         ASQ         ASQ
	// 		//  *Evict         ASQ         FEQ
	// 		//   StreamST      ASQ         ASQ
	// 		//   SO/DEV        ASQ         ASQ

	// 		`ifdef PRJ_SKYROS_INTERFACE//{
	// 		//L2 Imprecise External DAbort: Evcit for Skyros
	// 		if(|((l2_feq_comp_set_compdbidresp[`FEQ_MSB:0] | l2_feq_comp_set_compresp[`FEQ_MSB:0]) &
	// 			l2_feq_axi_wr_state_q[`FEQ_MSB:0] &
	// 			{`FEQ_SIZE{l2_rxrsp_resperr_q[1] | l2_rxrsp_resperr_q[0]}})) begin		//{

	// 				`ifdef MAIA
	// 				casez(l2_feq_axi_wr_state_q[`FEQ_MSB:0])		//Line is Dirty
	// 					24'h1:      imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq0_addr_q[44:0],1'b1};
	// 				24'h2:      imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq1_addr_q[44:0],1'b1};
	// 				24'h4:      imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq2_addr_q[44:0],1'b1};
	// 				24'h8:      imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq3_addr_q[44:0],1'b1};
	// 				24'h10:     imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq4_addr_q[44:0],1'b1};
	// 				24'h20:     imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq5_addr_q[44:0],1'b1};
	// 				24'h40:     imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq6_addr_q[44:0],1'b1};
	// 				24'h80:     imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq7_addr_q[44:0],1'b1};
	// 				24'h100:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq8_addr_q[44:0],1'b1};
	// 				24'h200:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq9_addr_q[44:0],1'b1};
	// 				24'h400:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq10_addr_q[44:0],1'b1};
	// 				24'h800:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq11_addr_q[44:0],1'b1};
	// 				24'h1000:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq12_addr_q[44:0],1'b1};
	// 				24'h2000:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq13_addr_q[44:0],1'b1};
	// 				24'h4000:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq14_addr_q[44:0],1'b1};
	// 				24'h8000:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq15_addr_q[44:0],1'b1};
	// 				24'h10000:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq16_addr_q[44:0],1'b1};
	// 				24'h20000:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq17_addr_q[44:0],1'b1};
	// 				24'h40000:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq18_addr_q[44:0],1'b1};
	// 				24'h80000:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq19_addr_q[44:0],1'b1};
	// 				24'h100000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq20_addr_q[44:0],1'b1};
	// 				24'h200000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq21_addr_q[44:0],1'b1};
	// 				24'h400000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq22_addr_q[44:0],1'b1};
	// 				24'h800000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq23_addr_q[44:0],1'b1};
	// 				default: ;
	// 				`else


	// 				`ifdef FEQ20
	// 				casez(l2_feq_axi_wr_state_q[`FEQ_MSB:0])		//Line is Dirty
	// 					20'h1:      imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq0_addr_q[44:0],1'b1};
	// 				20'h2:      imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq1_addr_q[44:0],1'b1};
	// 				20'h4:      imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq2_addr_q[44:0],1'b1};
	// 				20'h8:      imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq3_addr_q[44:0],1'b1};
	// 				20'h10:     imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq4_addr_q[44:0],1'b1};
	// 				20'h20:     imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq5_addr_q[44:0],1'b1};
	// 				20'h40:     imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq6_addr_q[44:0],1'b1};
	// 				20'h80:     imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq7_addr_q[44:0],1'b1};
	// 				20'h100:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq8_addr_q[44:0],1'b1};
	// 				20'h200:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq9_addr_q[44:0],1'b1};
	// 				20'h400:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq10_addr_q[44:0],1'b1};
	// 				20'h800:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq11_addr_q[44:0],1'b1};
	// 				20'h1000:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq12_addr_q[44:0],1'b1};
	// 				20'h2000:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq13_addr_q[44:0],1'b1};
	// 				20'h4000:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq14_addr_q[44:0],1'b1};
	// 				20'h8000:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq15_addr_q[44:0],1'b1};
	// 				20'h10000:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq16_addr_q[44:0],1'b1};
	// 				20'h20000:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq17_addr_q[44:0],1'b1};
	// 				20'h40000:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq18_addr_q[44:0],1'b1};
	// 				20'h80000:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq19_addr_q[44:0],1'b1};
	// 				default: ;
	// 				`else

	// 				casez(l2_feq_axi_wr_state_q[`FEQ_MSB:0])		//Line is Dirty
	// 					16'h1:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq0_addr_q[44:0],1'b1};
	// 				16'h2:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq1_addr_q[44:0],1'b1};
	// 				16'h4:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq2_addr_q[44:0],1'b1};
	// 				16'h8:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq3_addr_q[44:0],1'b1};
	// 				16'h10:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq4_addr_q[44:0],1'b1};
	// 				16'h20:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq5_addr_q[44:0],1'b1};
	// 				16'h40:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq6_addr_q[44:0],1'b1};
	// 				16'h80:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq7_addr_q[44:0],1'b1};
	// 				16'h100:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq8_addr_q[44:0],1'b1};
	// 				16'h200:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq9_addr_q[44:0],1'b1};
	// 				16'h400:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq10_addr_q[44:0],1'b1};
	// 				16'h800:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq11_addr_q[44:0],1'b1};
	// 				16'h1000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq12_addr_q[44:0],1'b1};
	// 				16'h2000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq13_addr_q[44:0],1'b1};
	// 				16'h4000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq14_addr_q[44:0],1'b1};
	// 				16'h8000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_feq15_addr_q[44:0],1'b1};
	// 				default: ;
	// 				`endif

	// 				`endif

	// 			endcase
	// 		end		//}
	// 		`else

	// 		//L2 Imprecise External DAbort: Write+StreamST+SO/DEV for both Skyros and ACE plus Evict for ACE
	// 		if( l2_bvalid_q &
	// 			(l2_bresp_q[1] | l2_bresp_q[0]) &

	// 			`ifndef MAIA
	// 			((l2_bid_q[5:0] =={3'b010,3'b100}) | (l2_bid_q[5:4] == 2'b00))) begin		//{
	// 			`else

	// 			((l2_bid_q[6:0] =={1'b1, 3'b010,3'b100}) | (l2_bid_q[6:5] == 2'b00))) begin		//{            // REVISIT - this doesn't work for detecting ACP writes anymore (dummy constant for now)
	// 			`endif

	// 			casez(l2_asq_bid_match[15:0])		//TnxID matched ASQ entry where the PhyAddr is for the abort
	// 				16'h1:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq0_addr_q[44:0],1'b1};
	// 			16'h2:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq1_addr_q[44:0],1'b1};
	// 			16'h4:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq2_addr_q[44:0],1'b1};
	// 			16'h8:    imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq3_addr_q[44:0],1'b1};
	// 			16'h10:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq4_addr_q[44:0],1'b1};
	// 			16'h20:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq5_addr_q[44:0],1'b1};
	// 			16'h40:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq6_addr_q[44:0],1'b1};
	// 			16'h80:   imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq7_addr_q[44:0],1'b1};
	// 			16'h100:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq8_addr_q[44:0],1'b1};
	// 			16'h200:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq9_addr_q[44:0],1'b1};
	// 			16'h400:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq10_addr_q[44:0],1'b1};
	// 			16'h800:  imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq11_addr_q[44:0],1'b1};
	// 			16'h1000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq12_addr_q[44:0],1'b1};
	// 			16'h2000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq13_addr_q[44:0],1'b1};
	// 			16'h4000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq14_addr_q[44:0],1'b1};
	// 			16'h8000: imp_data_abort6[`IMP_DABT_FIFO_ALL] <= {l2_asq15_addr_q[44:0],1'b1};
	// 			default: ;
	// 		endcase
	// 	end		//}
	// 		`endif//}

	// 		l2_cpu_dvalid_r2 <= `PRJ_DFF_DELAY l2_cpu_dvalid_r1;
	// 		l2_cpu_dbufid_r2 <= `PRJ_DFF_DELAY l2_cpu_dbufid_r1;
	// 	end		//}
	// end		//}
	
	//Detect GrpIdXing case
	
	
	reg [8:0]   inst_fifo_rd_ptr;
	reg [8:0]   inst_fifo_wr_ptr;
	reg [8:0]   load_fifo_rd_ptr;
	reg [8:0]   load_fifo_wr_ptr;
	
	reg [8:0]  i;
	reg [9:0]  j;
	
	reg [8:0] inst_fifo_wr_ptr_plus1;
	reg [8:0] load_fifo_wr_ptr_plus1;
	reg [4:0] st_va_fifo_wr_ptr_plus1;
	
	reg        gid_end_bit;
	
	reg [8:0]  ld_size;
	
	// Flops for load results
	// pipe the load result signals out to e5/w2

	`ifdef CORE_TESTBENCH//{
	`else

	reg   [`XM_AES_RTAG_INDEX-1:0]   lsu_resx_tag_w0;
	reg   [`XM_AES_RTAG_INDEX-1:0]   lsu_resx_tag_w1;
	reg           lsu_resx_tag_vld_w1;
	reg   [`XM_AES_RTAG_INDEX-1:0]   lsu_resy_tag_w0;
	reg   [`XM_AES_RTAG_INDEX-1:0]   lsu_resy_tag_w1;
	reg           lsu_resy_tag_vld_w1;
	`endif//}

	reg   [`XM_AES_RTAG_INDEX-1:0]   lsu_resx_tag_w2;
	reg           lsu_resx_tag_vld_w2;
	reg           lsu_resx_dw_w2;
	reg           lsu_resx_data_cancel_w2;
	reg   [`XM_AES_RTAG_INDEX-1:0]   lsu_resy_tag_w2;
	reg           lsu_resy_tag_vld_w2;
	reg           lsu_resy_dw_w2;
	reg           lsu_resy_data_cancel_w2;
	reg   [44:0]  ls_pa_ld_w2;
	reg   [44:0]  ls_pa_ld_w3;
	reg   [63:0]  ls_va_ld_w0;
	reg   [63:0]  ls_va_ld_w1;
	reg   [63:0]  ls_va_ld_w2;
	reg   [63:0]  ls_va_ld_w3;
	reg   [12:0]  ls_attr_ld_w2;
	reg   [12:0]  ls_attr_ld_w3;
	reg           sext_ld_w2;
	reg           big_endian_ld_w2;
	reg   [2:0]   element_size_ld_w2;
	reg           unal_second_ld_w2;
	reg           unal_second_ld_e4;
	reg           ld_res_matched;
	reg           ld_resx_matched;
	reg           ld_resy_matched;
	reg   [8:0]   ld_res_matched_entry;
	reg  [63:0]   ls_resx_data_swizzled_w2;
	reg  [63:0]   ls_resy_data_swizzled_w2;
	reg           spo_read_par_e2;
	reg           spo_read_par_w0;
	reg           spo_read_par_w1;
	reg           spo_read_par_w2;

	`ifdef CORE_TESTBENCH//{
	reg tb_load_tag_match_j;
	reg tb_load_tag_match_k;
	`endif//}

	
	//`ifdef EAGLE_OPCODE_COVERAGE//{
	//  // opcode coverage
	//  reg secure;
	//`endif//}
	
	always@(big_endian_ld_w2 or element_size_ld_w2 or lsu_resx_data_w2 or lsu_resy_data_w2) begin
		casez({big_endian_ld_w2,element_size_ld_w2[1:0]})
				3'b0?? : begin
					ls_resx_data_swizzled_w2[63:0] = lsu_resx_data_w2[63:0];
				ls_resy_data_swizzled_w2[63:0] = lsu_resy_data_w2[63:0];
			end
			3'b100 : begin
				ls_resx_data_swizzled_w2[63:0] = !element_size_ld_w2[2] ? lsu_resx_data_w2[63:0] :
					//AArch64 LDR Q with Element=128b: element_size_ld_w2[2:0]=3'b100
					{lsu_resy_data_w2[07:00],lsu_resy_data_w2[15:08],
					lsu_resy_data_w2[23:16],lsu_resy_data_w2[31:24],
					lsu_resy_data_w2[39:32],lsu_resy_data_w2[47:40],
					lsu_resy_data_w2[55:48],lsu_resy_data_w2[63:56]};
				ls_resy_data_swizzled_w2[63:0] = !element_size_ld_w2[2] ? lsu_resy_data_w2[63:0] :
					//AArch64 LDR Q with Element=128b: element_size_ld_w2[2:0]=3'b100
					{lsu_resx_data_w2[07:00],lsu_resx_data_w2[15:08],
					lsu_resx_data_w2[23:16],lsu_resx_data_w2[31:24],
					lsu_resx_data_w2[39:32],lsu_resx_data_w2[47:40],
					lsu_resx_data_w2[55:48],lsu_resx_data_w2[63:56]};
			end
			3'b101 : begin
				ls_resx_data_swizzled_w2[63:0] = {lsu_resx_data_w2[55:48],lsu_resx_data_w2[63:56],
					lsu_resx_data_w2[39:32],lsu_resx_data_w2[47:40],
					lsu_resx_data_w2[23:16],lsu_resx_data_w2[31:24],
					lsu_resx_data_w2[07:00],lsu_resx_data_w2[15:08]};
				ls_resy_data_swizzled_w2[63:0] = {lsu_resy_data_w2[55:48],lsu_resy_data_w2[63:56],
					lsu_resy_data_w2[39:32],lsu_resy_data_w2[47:40],
					lsu_resy_data_w2[23:16],lsu_resy_data_w2[31:24],
					lsu_resy_data_w2[07:00],lsu_resy_data_w2[15:08]};
			end
			3'b110 : begin
				ls_resx_data_swizzled_w2[63:0] = {lsu_resx_data_w2[39:32],lsu_resx_data_w2[47:40],
					lsu_resx_data_w2[55:48],lsu_resx_data_w2[63:56],
					lsu_resx_data_w2[07:00],lsu_resx_data_w2[15:08],
					lsu_resx_data_w2[23:16],lsu_resx_data_w2[31:24]};
				ls_resy_data_swizzled_w2[63:0] = {lsu_resy_data_w2[39:32],lsu_resy_data_w2[47:40],
					lsu_resy_data_w2[55:48],lsu_resy_data_w2[63:56],
					lsu_resy_data_w2[07:00],lsu_resy_data_w2[15:08],
					lsu_resy_data_w2[23:16],lsu_resy_data_w2[31:24]};
			end
			3'b111 : begin
				ls_resx_data_swizzled_w2[63:0] = {lsu_resx_data_w2[07:00],lsu_resx_data_w2[15:08],
					lsu_resx_data_w2[23:16],lsu_resx_data_w2[31:24],
					lsu_resx_data_w2[39:32],lsu_resx_data_w2[47:40],
					lsu_resx_data_w2[55:48],lsu_resx_data_w2[63:56]};
				ls_resy_data_swizzled_w2[63:0] = {lsu_resy_data_w2[07:00],lsu_resy_data_w2[15:08],
					lsu_resy_data_w2[23:16],lsu_resy_data_w2[31:24],
					lsu_resy_data_w2[39:32],lsu_resy_data_w2[47:40],
					lsu_resy_data_w2[55:48],lsu_resy_data_w2[63:56]};
			end
		endcase		// case ({big_endian_ld_w2,element_size_ld_w2[2:0]})
	end
	
	always @(posedge ck_gclkcr) begin
		if (reset) begin

			`ifdef CORE_TESTBENCH//{
			`else

			lsu_resx_tag_w0      <= `PRJ_DFF_DELAY {7{1'b0}};
			lsu_resx_tag_w1      <= `PRJ_DFF_DELAY {7{1'b0}};
			lsu_resx_tag_vld_w1  <= `PRJ_DFF_DELAY 1'b0;
			lsu_resy_tag_w0      <= `PRJ_DFF_DELAY {7{1'b0}};
			lsu_resy_tag_w1      <= `PRJ_DFF_DELAY {7{1'b0}};
			lsu_resy_tag_vld_w1  <= `PRJ_DFF_DELAY 1'b0;
			`endif//}

			lsu_resx_tag_w2      <= `PRJ_DFF_DELAY {7{1'b0}};
			lsu_resx_tag_vld_w2  <= `PRJ_DFF_DELAY 1'b0;
			lsu_resx_dw_w2       <= `PRJ_DFF_DELAY 1'b0;
			lsu_resx_data_cancel_w2 <= `PRJ_DFF_DELAY 1'b0;
			lsu_resy_tag_w2      <= `PRJ_DFF_DELAY {7{1'b0}};
			lsu_resy_tag_vld_w2  <= `PRJ_DFF_DELAY 1'b0;
			lsu_resy_dw_w2       <= `PRJ_DFF_DELAY 1'b0;
			lsu_resy_data_cancel_w2 <= `PRJ_DFF_DELAY 1'b0;
			ls_pa_ld_w2         <= `PRJ_DFF_DELAY {45{1'b0}};
			ls_pa_ld_w3         <= `PRJ_DFF_DELAY {45{1'b0}};
			ls_va_ld_w0         <= `PRJ_DFF_DELAY {64{1'b0}};
			ls_va_ld_w1         <= `PRJ_DFF_DELAY {64{1'b0}};
			ls_va_ld_w2         <= `PRJ_DFF_DELAY {64{1'b0}};
			ls_va_ld_w3         <= `PRJ_DFF_DELAY {64{1'b0}};
			ls_attr_ld_w2       <= `PRJ_DFF_DELAY {13{1'b0}};
			ls_attr_ld_w3       <= `PRJ_DFF_DELAY {13{1'b0}};
			sext_ld_w2          <= `PRJ_DFF_DELAY 1'b0;
			big_endian_ld_w2    <= `PRJ_DFF_DELAY 1'b0;
			element_size_ld_w2  <= `PRJ_DFF_DELAY 3'b000;
			unal_second_ld_w2   <= `PRJ_DFF_DELAY 1'b0;
			unal_second_ld_e4   <= `PRJ_DFF_DELAY 1'b0;
			spo_read_par_e2     <= `PRJ_DFF_DELAY 1'b0;
			spo_read_par_w0     <= `PRJ_DFF_DELAY 1'b0;
			spo_read_par_w1     <= `PRJ_DFF_DELAY 1'b0;
			spo_read_par_w2     <= `PRJ_DFF_DELAY 1'b0;
		end else begin		// if (reset)

			`ifdef CORE_TESTBENCH//{
			`else

			lsu_resx_tag_w0      <= `PRJ_DFF_DELAY dstx_tag_ld_e2;
			lsu_resx_tag_w1      <= `PRJ_DFF_DELAY lsu_resx_tag_w0;
			lsu_resx_tag_vld_w1  <= `PRJ_DFF_DELAY lsu_resx_tag_vld_w0;
			lsu_resy_tag_w0      <= `PRJ_DFF_DELAY dsty_tag_ld_e2;
			lsu_resy_tag_w1      <= `PRJ_DFF_DELAY lsu_resy_tag_w0;
			lsu_resy_tag_vld_w1  <= `PRJ_DFF_DELAY lsu_resy_tag_vld_w0;
			`endif//}

			lsu_resx_tag_w2      <= `PRJ_DFF_DELAY lsu_resx_tag_w1;
			lsu_resx_tag_vld_w2  <= `PRJ_DFF_DELAY lsu_resx_tag_vld_w1 && ~strex_force_ld_e4;
			lsu_resx_dw_w2       <= `PRJ_DFF_DELAY lsu_resx_dw_w1;
			lsu_resx_data_cancel_w2 <= `PRJ_DFF_DELAY lsu_resx_data_cancel_w1;
			lsu_resy_tag_w2      <= `PRJ_DFF_DELAY lsu_resy_tag_w1;
			lsu_resy_tag_vld_w2  <= `PRJ_DFF_DELAY lsu_resy_tag_vld_w1;
			lsu_resy_dw_w2       <= `PRJ_DFF_DELAY lsu_resy_dw_w1;
			lsu_resy_data_cancel_w2 <= `PRJ_DFF_DELAY lsu_resy_data_cancel_w1;
			ls_pa_ld_w2         <= `PRJ_DFF_DELAY lsu_pa_ld_e4;
			ls_pa_ld_w3         <= `PRJ_DFF_DELAY ls_pa_ld_w2;
			ls_va_ld_w0         <= `PRJ_DFF_DELAY lsu_va_ld_e2;
			ls_va_ld_w1         <= `PRJ_DFF_DELAY ls_va_ld_w0;
			ls_va_ld_w2         <= `PRJ_DFF_DELAY ls_va_ld_w1;
			ls_va_ld_w3         <= `PRJ_DFF_DELAY ls_va_ld_w2;
			ls_attr_ld_w2       <= `PRJ_DFF_DELAY {lsu_shared_attr_ld_e4[1:0],lsu_cache_attr_ld_e4[2:0],lsu_page_attr_ld_e4[7:0]};
			ls_attr_ld_w3       <= `PRJ_DFF_DELAY ls_attr_ld_w2;
			sext_ld_w2          <= `PRJ_DFF_DELAY sext_ld_e4;
			big_endian_ld_w2    <= `PRJ_DFF_DELAY big_endian_ld_e4;
			element_size_ld_w2  <= `PRJ_DFF_DELAY element_size_ld_e4[2:0];
			unal_second_ld_w2   <= `PRJ_DFF_DELAY unal_second_ld_e4;
			unal_second_ld_e4   <= `PRJ_DFF_DELAY unal_second_ld_e3;
			spo_read_par_e2     <= `PRJ_DFF_DELAY spo_read_par_s2;
			spo_read_par_w0     <= `PRJ_DFF_DELAY spo_read_par_e2;
			spo_read_par_w1     <= `PRJ_DFF_DELAY spo_read_par_w0;
			spo_read_par_w2     <= `PRJ_DFF_DELAY spo_read_par_w1;
		end
	end
	
	// every DS_FLUSH_TYPE should appear here, either as a term ORed in, or as a comment that it's
	// skipped
	assign ds_exception_flush_u2 = ds_flush_u2 &&
		(ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_RESET ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PIMP_EXT_DABORT ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PFIQ ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PIRQ ||
		//Debug Type:catch those to send debug_state to Tarmac trace
		ds_flush_type_u2[5:0] == `PRJ_DSU_FLUSH_TYPE_DBG_HALT_REQ ||
		ds_flush_type_u2[5:0] == `PRJ_DSU_FLUSH_TYPE_DBG_HALT_EXIT ||
		ds_flush_type_u2[5:0] == `PRJ_DSU_FLUSH_TYPE_WTCHPNT ||
		ds_flush_type_u2[5:0] == `PRJ_DSU_FLUSH_TYPE_BRKPNT_REGHIT ||
		ds_flush_type_u2[5:0] == `PRJ_DSU_FLUSH_TYPE_BRKPNT_SNGLSTP ||
		ds_flush_type_u2[5:0] == `PRJ_DSU_FLUSH_TYPE_HLT_INST ||
		ds_flush_type_u2[5:0] == `PRJ_DSU_FLUSH_TYPE_RST_CATCH ||
		ds_flush_type_u2[5:0] == `PRJ_DSU_FLUSH_TYPE_EXC_CATCH ||
		ds_flush_type_u2[5:0] == `PRJ_DSU_FLUSH_TYPE_SW_ACC_TRAP ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_BRKPNT_VECTRP ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_BRKPNT_INST ||
		//
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PRC_INT_PABORT ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PRC_PC_PABORT ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PRC_EXT_PABORT ||
		// skipped BAD_BRN
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_UNDEF ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_HVC ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_SVC ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_SMC ||
		// skipped WFI
		// skipped WFE
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_CHKA ||
		// skipped MEM_NUKE
		// skipped SWDW_NUKE
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_NULL_CHK ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PRC_INT_DABORT ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PRC_EXT_DABORT ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PRC_SP_DABORT ||
		// skipped SLNT_BRN
		// skipped ISB
		// skipped ISBLITE
		// skipped ISBLITEX
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_HYP_TRAP ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_MON_TRAP ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_VIMP_EXT_DABORT ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_VFIQ ||
		ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_VIRQ);
	
	wire sodevnc_allocated;
	
	assign sodevnc_allocated = |iq_ld_alloc_fb_e4[1:0] && sodev_ex_ld_e4;
	
	
	wire       aes_dstx_vld_0p2;
	wire [1:0] aes_dstx_cnt_0p2;
	wire       aes_dsty_vld_0p2;
	wire [1:0] aes_dsty_cnt_0p2;
	
	assign aes_dstx_vld_0p2 = resq_wrenx_0p2 && ((dstx_type_0p2_q[2:0]==3'b000 && dstx_atag_0p2_q[5:1]!=5'b10100) ||
		(dstx_type_0p2_q[1:0]==2'b01 && dstx_atag_0p2_q[5:1]!=5'b10000));
	assign aes_dstx_cnt_0p2[1] = aes_dstx_vld_0p2 & dstx_dw_0p2_q;
	assign aes_dstx_cnt_0p2[0] = aes_dstx_vld_0p2 & ~dstx_dw_0p2_q;
	
	assign aes_dsty_vld_0p2 = resq_wreny_0p2 && ((dsty_type_0p2_q[2:0]==3'b000 && dsty_atag_0p2_q[5:1]!=5'b10100) ||
		(dsty_type_0p2_q[1:0]==2'b01 && dsty_atag_0p2_q[5:1]!=5'b10000));
	assign aes_dsty_cnt_0p2[1] = aes_dsty_vld_0p2 & dsty_dw_0p2_q;
	assign aes_dsty_cnt_0p2[0] = aes_dsty_vld_0p2 & ~dsty_dw_0p2_q;
	
	wire       aes_dstx_vld_1p2;
	wire [1:0] aes_dstx_cnt_1p2;
	wire       aes_dsty_vld_1p2;
	wire [1:0] aes_dsty_cnt_1p2;
	
	assign aes_dstx_vld_1p2 = resq_wrenx_1p2 && ((dstx_type_1p2_q[2:0]==3'b000 && dstx_atag_1p2_q[5:1]!=5'b10100) ||
		(dstx_type_1p2_q[1:0]==2'b01 && dstx_atag_1p2_q[5:1]!=5'b10000));
	assign aes_dstx_cnt_1p2[1] = aes_dstx_vld_1p2 & dstx_dw_1p2_q;
	assign aes_dstx_cnt_1p2[0] = aes_dstx_vld_1p2 & ~dstx_dw_1p2_q;
	
	assign aes_dsty_vld_1p2 = resq_wreny_1p2 && ((dsty_type_1p2_q[2:0]==3'b000 && dsty_atag_1p2_q[5:1]!=5'b10100) ||
		(dsty_type_1p2_q[1:0]==2'b01 && dsty_atag_1p2_q[5:1]!=5'b10000));
	assign aes_dsty_cnt_1p2[1] = aes_dsty_vld_1p2 & dsty_dw_1p2_q;
	assign aes_dsty_cnt_1p2[0] = aes_dsty_vld_1p2 & ~dsty_dw_1p2_q;
	
	wire       aes_dstx_vld_2p2;
	wire [1:0] aes_dstx_cnt_2p2;
	wire       aes_dsty_vld_2p2;
	wire [1:0] aes_dsty_cnt_2p2;
	
	assign aes_dstx_vld_2p2 = resq_wrenx_2p2 && ((dstx_type_2p2_q[2:0]==3'b000 && dstx_atag_2p2_q[5:1]!=5'b10100) ||
		(dstx_type_2p2_q[1:0]==2'b01 && dstx_atag_2p2_q[5:1]!=5'b10000));
	assign aes_dstx_cnt_2p2[1] = aes_dstx_vld_2p2 & dstx_dw_2p2_q;
	assign aes_dstx_cnt_2p2[0] = aes_dstx_vld_2p2 & ~dstx_dw_2p2_q;
	
	assign aes_dsty_vld_2p2 = resq_wreny_2p2 && ((dsty_type_2p2_q[2:0]==3'b000 && dsty_atag_2p2_q[5:1]!=6'b10100) ||
		(dsty_type_2p2_q[1:0]==2'b01 && dsty_atag_2p2_q[5:1]!=5'b10000));
	assign aes_dsty_cnt_2p2[1] = aes_dsty_vld_2p2 & dsty_dw_2p2_q;
	assign aes_dsty_cnt_2p2[0] = aes_dsty_vld_2p2 & ~dsty_dw_2p2_q;
	
	////---------------------- Revised by sbc@2014-03-12 11:03 BEGIN----------------------
	wire       aes_dstx_vld_3p2;
	wire [1:0] aes_dstx_cnt_3p2;
	wire       aes_dsty_vld_3p2;
	wire [1:0] aes_dsty_cnt_3p2;
	
	assign aes_dstx_vld_3p2 = resq_wrenx_3p2 && ((dstx_type_3p2_q[2:0]==3'b000 && dstx_atag_3p2_q[5:1]!=5'b10100) ||
		(dstx_type_3p2_q[1:0]==2'b01 && dstx_atag_3p2_q[5:1]!=5'b10000));
	assign aes_dstx_cnt_3p2[1] = aes_dstx_vld_3p2 & dstx_dw_3p2_q;
	assign aes_dstx_cnt_3p2[0] = aes_dstx_vld_3p2 & ~dstx_dw_3p2_q;
	
	assign aes_dsty_vld_3p2 = resq_wreny_3p2 && ((dsty_type_3p2_q[2:0]==3'b000 && dsty_atag_3p2_q[5:1]!=6'b10100) ||
		(dsty_type_3p2_q[1:0]==2'b01 && dsty_atag_3p2_q[5:1]!=5'b10000));
	assign aes_dsty_cnt_3p2[1] = aes_dsty_vld_3p2 & dsty_dw_3p2_q;
	assign aes_dsty_cnt_3p2[0] = aes_dsty_vld_3p2 & ~dsty_dw_3p2_q;
	////---------------------- Revised by sbc@2014-03-12 11:03 END------------------------
	
	reg       resx_tag_vld;
	reg [`XM_AES_RTAG_INDEX-1:0] resx_tag;
	reg       resy_tag_vld;
	reg [`XM_AES_RTAG_INDEX-1:0] resy_tag;
	
	////---------------------- Revised by sbc@2014-04-08 11:18 BEGIN----------------------

	`ifdef RAVEN_DEBUG
	int     undefine_flag;
	initial begin
		undefine_flag=0;
	end
	`endif //RAVEN_DEBUG


	`ifdef RAVEN_COSIM
	int 	inst_flag;
	int     finish_flag;
	reg [511:0] inst_buff;
	final begin
		///-------------------------------------------------------------------
		inst_flag=verify_InstStream(inst_mem_ptr);
		if(inst_flag==1) begin
			$display("COSIM_ERROR: INSTRUCTION CHECK ERROR!");
			$finish;
		end
		else if(inst_flag==2) begin
			$display("COSIM_ERROR: REG CHECK ERROR!");
			$finish;
		end
		else if(inst_flag==3) begin
			$display("COSIM_ERROR: MEM CHECK ERROR!");
			$finish;
		end
		else if(inst_flag==5) begin
			$display("COSIM_WARNING: INCOMPLETE CHECK!");
		end
		else if(inst_flag==7) begin
			$display("COSIM_ERROR: UNDEFINE INSTRUCTION!");
			$finish;
		end
		///-------------------------------------------------------------------
		aes_flag0=verify_register(aes_mem_ptr);
		if(aes_flag0==2) begin
			$display("COSIM_ERROR: REG CHECK ERROR!");
			$finish;
		end
		else if(aes_flag0==1) begin
			$display("COSIM_ERROR: INSTRUCTION CHECK ERROR!");
			$finish;
		end
		else if(aes_flag0==3) begin
			$display("COSIM_ERROR: MEM CHECK ERROR!");
			$finish;
		end
		else if(aes_flag0==5) begin
			$display("COSIM_WARNING: INCOMPLETE CHECK!");
		end
		///-------------------------------------------------------------------
		finish_flag=verify_finish();
		if(finish_flag==0) begin
			$finish;
		end
		else if(finish_flag==8) begin
			$display("COSIM_ERROR: UNFINISHED!");
			$finish;
		end
	end
	`endif //RAVEN_COSIM

	////---------------------- Revised by sbc@2014-04-08 11:18 END------------------------
		
	always @(posedge ck_gclkcr) begin
		if(reset) begin
			fusion_opc_fifo_rd_ptr = 0;
			fusion_opc_fifo_wr_ptr = 0;
			opc_fifo_rd_ptr = 0;
			opc_fifo_wr_ptr = 0;
			in_preamble = 1'b0;
			skip_preamble = 1'b0;
			inst_fifo_rd_ptr = 0;
			inst_fifo_wr_ptr = 0;
			load_fifo_rd_ptr = 0;
			load_fifo_wr_ptr = 0;
			ld_res_matched        = 0;
			ld_res_matched_entry  = 0;
			for(j=0;j<INST_FIFO_SIZE;j++) begin
				inst_fifo[j] = 0;
				load_fifo[j] = 0;
				load_fifo_e[j] = 0;
			end
		end
		else begin
			// handle flushes
			if(flush_u2) begin
				if((verbosity>0)) $display("detected flush_u2=1\n");
				
				//Save off Flushed Instruction information for GroupIdXing case. Only DS Flush not BX Flush.
				if(ds_exception_flush_u2) begin
					inst_fifo_flushed = 'b0;
					if(inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_GRPIDXING] == 1'b1) begin		//This Instruction span across 2 Group IDs
						//2nd Group ID Encounter Internal DAbort or Watchpoint(implicit DAbort)
						if((ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_PRC_INT_DABORT || ds_flush_type_u2[5:0]==`PRJ_DSU_FLUSH_TYPE_WTCHPNT) &&
							( flush_gid_u2 ==  inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_GID_FULL]))		//2nd GID got flushed
							begin
								inst_fifo_flushed = inst_fifo[inst_fifo_rd_ptr];
							if(verbosity) $display("GrpIdXing=%d with ST Bytes=%h", inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_GRPIDXING],
								inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_ST_BYTES]);
							if(verbosity) $display("Dispatch Exception! Saving off Flushed Instruction info.");
						end
						else begin
							inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_GRPIDXING] = 1'b0;		//Clear: it's 1st group got abort or other exception
						end
					end
				end
				
				
				//Always keep track of the flushed GID which can be used to flush FIFOs in the C/C++ side
				inst_fifo_flushed[`INST_FIFO_GID_FULL] = inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_GID_FULL];
				
				
				// decrement inst_fifo_wr_ptr until i find a group older than the flushed group (or until I hit the rd_ptr)
				// clear the inst_fifo entries that are flushed
				inst_fifo_wr_ptr_plus1[8:0] = inst_fifo_wr_ptr[8:0] + 1;
				while(inst_fifo_wr_ptr_plus1!=inst_fifo_rd_ptr &&
					(inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]==0 ||
					((((inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_WRAP]^flush_gid_u2[6]) &&
					(flush_gid_u2[5:0]>inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID])) ||
					((inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_WRAP]==flush_gid_u2[6]) &&
					flush_gid_u2[5:0]<=inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID]))))) begin
						if((verbosity>0)) $display("while loop : wr_ptr_p1=%d wr_ptr=%d rd_ptr=%d\n",inst_fifo_wr_ptr_plus1,inst_fifo_wr_ptr,inst_fifo_rd_ptr);
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD] = 0;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMPLETE] = 0;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMMITTED] = 0;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] = 0;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LD_BYTES] = 0;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_AES_CNT] = 0;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_PSR_CNT] = 0;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_SPW_CNT] = 0;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_FUSEDPARENT] = 0;		//Prevent false Fusion indication
					
					// clear opcode valid unless this is the oldest instruction in the machine (wr_ptr=rd_ptr) and this is a
					// ds_exception flush.  OPC_VLD is only important when there's a dsu_flush on an instruction that hasn't completed yet
					// (abort/wpt/nullcheck on noncompleted ld/st).  In that case, the opc_fifo hasn't been popped yet for the
					// ld/st, so have to pop it on the dsu_flush
					if(inst_fifo_wr_ptr!=inst_fifo_rd_ptr || !ds_exception_flush_u2) begin
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPC_VLD] = 0;
					end
					inst_fifo_wr_ptr--;
					inst_fifo_wr_ptr_plus1[8:0] = inst_fifo_wr_ptr[8:0] + 1;
				end
				// found the last written opcode that wasn't flushed and is COMPLETE, so increment to the first empty entry
				// SLNBRN preamble followed by another exception could advance inst_fifo_wr_ptr while the entry pointed by it is still not COMPLETE
				if((inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD] && inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMPLETE]) ||		//is COMPLETE
					(inst_fifo_wr_ptr_plus1==inst_fifo_rd_ptr)) inst_fifo_wr_ptr++;		//Empty+Reset Case
				
				// clear the load_fifo entries that are flushed
				load_fifo_wr_ptr_plus1[8:0] = load_fifo_wr_ptr[8:0] + 1;
				while(load_fifo_wr_ptr_plus1!=load_fifo_rd_ptr &&
					(load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_VLD]==0 ||
					(((load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_GID_WRAP]^flush_gid_u2[6]) &&
					(flush_gid_u2[5:0]>load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_GID])) ||
					((load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_GID_WRAP]==flush_gid_u2[6]) &&
					flush_gid_u2[5:0]<=load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_GID])))) begin
						load_fifo[load_fifo_wr_ptr] = 0;
					load_fifo_wr_ptr--;
					load_fifo_wr_ptr_plus1[8:0] = load_fifo_wr_ptr[8:0] + 1;
					if (verbosity>0) $display("flushed load_fifo[%0d]",load_fifo_wr_ptr);
				end
				load_fifo_wr_ptr++;
				
				// exception handling on dsu_flush
				if(ds_exception_flush_u2) begin
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD] = 1;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_EN] = 1'b1;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_TYP] = ds_flush_type_u2[5:0];
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_STG2_EXC] = stg2_exc_u2;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ALGN_EXC] = algn_exc_u2;
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_SP_ALGN_EXC] = sp_algn_exc_u2;
					
					// if cpu was powered down, have to reset ISS regfiles
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_PWR_CYC] = power_cycle_seen;
					if(power_cycle_seen)
						power_cycle_seen = 1'b0;
					
					// OPC_VLD is only important when there's a dsu_flush on an instruction that hasn't completed yet
					// (abort/wpt/nullcheck on noncompleted ld/st).  In that case, the opc_fifo hasn't been popped yet for the
					// ld/st, so have to pop it on the dsu_flush
					if(!inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPC_VLD]) begin
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_FUSEDPARENT] = fusion_opc_fifo[fusion_opc_fifo_rd_ptr];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_IFU_PCALGN_ABT_PEND] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_IFU_PCALGN_ABT_PEND];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LB_END] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_LB_END];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LB_START] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_LB_START];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_TBIT]   = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_TBIT];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ISIZE]   = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_ISIZE];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPCODE] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_OPCODE];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPC_VLD] = 1'b1;
					end
				end		// if (ds_flush_u2)
				
				// if there's a flush, clear the entire opcode fifo
				opc_fifo_rd_ptr = opc_fifo_wr_ptr;
				fusion_opc_fifo_rd_ptr = fusion_opc_fifo_wr_ptr;
				
			end
			
			
			// set in_preamble state if i see dsu_prestart
			// currently only use this to determine if uop is a preamble uop.  only sample itbits if it's not a
			// preamble uop
			if(dsu_prestart) begin
				in_preamble = 1'b1;
			end
			
			//Set after seeing a SLNT_BRN
			if(ds_flush_u2 && (ds_flush_type_u2 == `PRJ_DSU_FLUSH_TYPE_SLNT_BRN)) begin
				skip_preamble = 1'b1;
			end
			if(skip_preamble && dsu_ia_restart) begin
				skip_preamble = 1'b0;
			end
			
			if(ifu_vld_0d1 & dec_genq_1free) begin
				if((verbosity>0)) $display("pushing opcode 0x%08x, tbit=%x, size=%x\n",
					{ifu_inst_h_0d1[31:16],ifu_inst_l_0d1[15:0]},ifu_tbit_0d1,ifu_size_0d1);
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_FUSEDPARENT] = 1'b0;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_IFU_PCALGN_ABT_PEND] = ifu_pcalgn_abt_pend;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_ISIZE]    = ifu_size_0d1;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_TBIT]     = ifu_tbit_0d1;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_OPCODE]   = {ifu_inst_h_0d1[31:16],ifu_inst_l_0d1[15:0]};
				opc_fifo_wr_ptr += 1;
			end
			if(ifu_vld_1d1 & dec_genq_2free) begin
				if((verbosity>0)) $display("pushing opcode 0x%08x, tbit=%x, size=%x\n",
					{ifu_inst_h_1d1[31:16],ifu_inst_l_1d1[15:0]},ifu_tbit_1d1,ifu_size_1d1);
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_FUSEDPARENT] = 1'b0;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_IFU_PCALGN_ABT_PEND] = ifu_pcalgn_abt_pend;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_ISIZE]    = ifu_size_1d1;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_TBIT]     = ifu_tbit_1d1;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_OPCODE]   = {ifu_inst_h_1d1[31:16],ifu_inst_l_1d1[15:0]};
				opc_fifo_wr_ptr += 1;
			end
			if(ifu_vld_2d1 & dec_genq_3free) begin
				if((verbosity>0)) $display("pushing opcode 0x%08x, tbit=%x, size=%x\n",
					{ifu_inst_h_2d1[31:16],ifu_inst_l_2d1[15:0]},ifu_tbit_2d1,ifu_size_2d1);
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_FUSEDPARENT] = 1'b0;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_IFU_PCALGN_ABT_PEND] = ifu_pcalgn_abt_pend;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_ISIZE]    = ifu_size_2d1;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_TBIT]     = ifu_tbit_2d1;
				opc_fifo[opc_fifo_wr_ptr][`OPC_FIFO_OPCODE]   = {ifu_inst_h_2d1[31:16],ifu_inst_l_2d1[15:0]};
				opc_fifo_wr_ptr += 1;
			end
			
			//Instruction Fusion Information{
			//Process R2 information with those R2 signals pipelined from D1!
			//Fusion Parent Indication: fused_parent_2r2 fused_parent_1r2 fused_parent_0r2
			//                                  0                0                1
			//                                  0                1                0
			//                                  1                0                0
			//                                  1                0                1
			//                                  other combinations are not possible
			
			if(ok_uop_vld_0r2 & inst_end_0r2 & dsu_dispq_1free & ~id_preamble_0r2) begin
				if((verbosity>0)) $display("Capture opcode 0x%08x, tbit=%x, size=%x FuseParent=%d into FUSION_OPC_FIFO(%d)\n", inst_opcode_0r2,tbit_0r2, size_0r2,fused_parent_0r2,fusion_opc_fifo_wr_ptr);
				fusion_opc_fifo[fusion_opc_fifo_wr_ptr] = fused_parent_0r2;
				fusion_opc_fifo_wr_ptr++;
			end
			if(ok_uop_vld_1r2 & inst_end_1r2 & dsu_dispq_2free & ~id_preamble_1r2) begin
				if((verbosity>0)) $display("Capture opcode 0x%08x, tbit=%x, size=%x FuseParent=%d into FUSION_OPC_FIFO(%d)\n", inst_opcode_1r2,tbit_1r2, size_1r2,fused_parent_1r2,fusion_opc_fifo_wr_ptr);
				fusion_opc_fifo[fusion_opc_fifo_wr_ptr] = fused_parent_1r2;
				fusion_opc_fifo_wr_ptr++;
			end
			if(ok_uop_vld_2r2 & inst_end_2r2 & dsu_dispq_3free & ~id_preamble_2r2) begin
				if((verbosity>0)) $display("Capture opcode 0x%08x, tbit=%x, size=%x FuseParent=%d into FUSION_OPC_FIFO(%d)\n", inst_opcode_2r2,tbit_2r2, size_2r2,fused_parent_2r2,fusion_opc_fifo_wr_ptr);
				fusion_opc_fifo[fusion_opc_fifo_wr_ptr] = fused_parent_2r2;
				fusion_opc_fifo_wr_ptr++;
			end
			////---------------------- Revised by sbc@2014-03-12 11:04 BEGIN----------------------
			if(ok_uop_vld_3r2 & inst_end_3r2 & dsu_dispq_4free & ~id_preamble_3r2) begin
				if((verbosity>0)) $display("Capture opcode 0x%08x, tbit=%x, size=%x FuseParent=%d into FUSION_OPC_FIFO(%d)\n", inst_opcode_3r2,tbit_3r2, size_3r2,fused_parent_3r2,fusion_opc_fifo_wr_ptr);
				fusion_opc_fifo[fusion_opc_fifo_wr_ptr] = fused_parent_3r2;
				fusion_opc_fifo_wr_ptr++;
			end
			////---------------------- Revised by sbc@2014-03-12 11:04 END------------------------
			//Instruction Fusion Information}
			
			// add any new uops in P2 to the inst_fifo, have to do this three times, for slot 0, slot 1 and slot 2
			if((verbosity>0)) $display("look for new uops in p2\n");
			if(uop_vld_0p2_q) begin
				// write the gid
				//GrpIdXing Case: Clear INST_FIFO_GRPIDXING when allocating inst_fifo
				//                Set when GID is changing when inst_end is not asserted and inst_fifo GID matches previous cycle GID
				if(inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]==0) inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b0;
				if(!in_preamble && !inst_end_0p2_q && inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]
					&& ((gid_0p2_q == (gid_0p3 + 7'b0000001)) ||
					(gid_0p2_q == 7'b1000000 && gid_0p3 == 7'b0100111) ||
					(gid_0p2_q == 7'b0000000 && gid_0p3 == 7'b1100111))
					&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] != 8'b0000000
					&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] == gid_0p3) begin
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b1;
					if(verbosity) $display("GrpIdXing Case Detected!");
				end		// if(!inst_end_0p2_q )
				
				
				//This detection must be placed before inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD] assignment
				if(inst_end_0p2_q && inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]) begin
					if(inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] != gid_0p2_q[6:0])
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_SPLIT] = 1'b0;
				end
				
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD] = 1;
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMMITTED] = 1'b0;
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] = gid_0p2_q[6:0];
				
				
				// update ITBITS as long as it's not a preamble uop
				if(~in_preamble && ~itnoadv_0p2_q) begin		//
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ITBITS] = uop_itbits_0p2_q[7:0];
				end
				else if(itnoadv_0p2_q) begin
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ITBITS] = 8'b0;
				end
				
				// update AES result count for current instruction
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_AES_CNT] += aes_dstx_cnt_0p2[1:0] + aes_dsty_cnt_0p2[1:0];
				
				// update PSR result count for current instruction
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_PSR_CNT] += resq_wrenp_0p2;
				
				// update SPW count
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_SPW_CNT] += (spr_uop_vld_0p2_q & !uop_ctl_0p2_q[54]);		// [54]=NOP
				
				// update # of store bytes expected for current instruction
				if(ls0_uop_vld_0p2_q || ls1_uop_vld_0p2_q) begin
					if(uop_ctl_0p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_STORE) begin
						case (uop_ctl_0p2_q[`PRJ_CTL_SIZE_3])
								`PRJ_SIZE_B  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 1;
								`PRJ_SIZE_H  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 2;
								`PRJ_SIZE_3  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 3;
								`PRJ_SIZE_W  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 4;
								`PRJ_SIZE_6  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 6;
								`PRJ_SIZE_D  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 8;
								`PRJ_SIZE_12 : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 12;
								`PRJ_SIZE_16 : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 16;
							endcase		// case (uop_ctl_0p2_q[`PRJ_CTL_SIZE_3])
							//Number of Memory Op associated with this Ld/St instruction
							inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_NMOP] += 1;		//This number will indicate how many LS uops are issued before a flush or retirement
						//Store memory size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ESIZE] = {uop_ctl_0p2_q[`PRJ_CTL_ELEM_SIZE_B3],uop_ctl_0p2_q[`PRJ_CTL_ELEM_SIZE_2]};
						//Store element size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_MSIZE] = uop_ctl_0p2_q[`PRJ_CTL_SIZE_3];
						
						// see if this is STREX
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_STREX] = uop_ctl_0p2_q[`PRJ_CTL_ARM2EXT_EXCLUSIVE];
					end		// if (uop_ctl_0p2_q[`CTL_STORE])
				end
				
				// update # of load bytes expected for current instruction
				// also grab tag information so we can compare later
				if(ls0_uop_vld_0p2_q || ls1_uop_vld_0p2_q) begin
					if(uop_ctl_0p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_LOAD

						`ifdef CORE_TESTBENCH//{
						|| (uop_ctl_0p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_MOV_ADD && !uop_ctl_0p2_q[`PRJ_CTL_NULL_CHECK])
						`endif//}

						) begin
							case (uop_ctl_0p2_q[`PRJ_CTL_SIZE_3])
								`PRJ_SIZE_B  : ld_size = 1;
								`PRJ_SIZE_H  : ld_size = 2;
								`PRJ_SIZE_3  : ld_size = 3;
								`PRJ_SIZE_W  : ld_size = 4;
								`PRJ_SIZE_6  : ld_size = 6;
								`PRJ_SIZE_D  : ld_size = 8;
								`PRJ_SIZE_12 : ld_size = 12;
								`PRJ_SIZE_16 : ld_size = 16;
							endcase		// case (uop_ctl_0p2_q[`PRJ_CTL_SIZE_3])
							//Number of Memory Op associated with this Ld/St instruction
							inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_NMOP] += 1;		//This number will indicate how many LS uops are issued before a flush or retirement
						//Store memory size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ESIZE] = {uop_ctl_0p2_q[`PRJ_CTL_ELEM_SIZE_B3],uop_ctl_0p2_q[`PRJ_CTL_ELEM_SIZE_2]};
						//Store element size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_MSIZE] = uop_ctl_0p2_q[`PRJ_CTL_SIZE_3];
						
						if (verbosity>0) $display("new load fifo entry 0p2, wr_ptr:%0d",load_fifo_wr_ptr);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LD_BYTES] += ld_size;
						
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_VLD]       = 1'b1;

						`ifdef CORE_TESTBENCH//{
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_VA_VLD]    = uop_ctl_0p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_MOV_ADD ? 1'b1 : 1'b0;
						`endif//}

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_VLD]  = dstx_tag_vld_0p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_RTAG]  = dstx_rtag_0p2_q;

						`ifdef RESULTQ_NOT_128
						load_fifo_e[load_fifo_wr_ptr][0]  = dstx_rtag_0p2_q[7];
						`endif

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_ATAG]  = dstx_atag_0p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_TYPE]  = dstx_type_0p2_q;
						//MAIA: late uop cracking - If we see both LS/SX clusters have valid uops, it's a  LS/SX late cracking case
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_VLD]  =  sxj_uop_vld_0p2_q | sxk_uop_vld_0p2_q ? 1'b0 : dsty_tag_vld_0p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_RTAG]  = dsty_rtag_0p2_q;

						`ifdef RESULTQ_NOT_128
						load_fifo_e[load_fifo_wr_ptr][1]  = dsty_rtag_0p2_q[7];
						`endif

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_ATAG]  = dsty_atag_0p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_TYPE]  = dsty_type_0p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_GID_FULL]  = gid_0p2_q[6:0];
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_LD_SIZE]   = ld_size;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_INSTR]     = inst_fifo_wr_ptr;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_UNALIGNED]= 1'b0;
						load_fifo_wr_ptr++;
					end		// if (uop_ctl_0p2_q[`CTL_LOAD])
				end
				
				
				
				// if this is the last uop of an instruction, record ia, pop opcode, and increment inst_fifo_wr_ptr
				
				if((inst_end_0p2_q || pre_end_0p2_q) && ~skip_preamble) begin
					
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMPLETE] = 1'b1;
					
					if(~pre_end_0p2_q) begin
						if((verbosity>0)) $display("popping opcode 0x%08x from OPC_FIFO(%d)/FUSION_OPC_FIFO(%d) to INST_FIFO(%d)\n",opc_fifo[opc_fifo_rd_ptr],opc_fifo_rd_ptr,inst_fifo_wr_ptr,fusion_opc_fifo_rd_ptr);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_FUSEDPARENT] = fusion_opc_fifo[fusion_opc_fifo_rd_ptr];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_IFU_PCALGN_ABT_PEND] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_IFU_PCALGN_ABT_PEND];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LB_END] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_LB_END];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LB_START] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_LB_START];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_TBIT]   = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_TBIT];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ISIZE]   = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_ISIZE];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPCODE] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_OPCODE];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPC_VLD] = 1'b1;
						opc_fifo_rd_ptr++;
						fusion_opc_fifo_rd_ptr++;
					end
					//Update Store byte information from the GrpIdXing case that was flushed earlier
					else if(pre_end_0p2_q && inst_fifo_flushed[`INST_FIFO_GRPIDXING]
						&& inst_fifo_flushed[`INST_FIFO_VLD]
						&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_EN]
						&& (   inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_TYP] == `PRJ_DSU_FLUSH_TYPE_PRC_INT_DABORT
						|| inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_TYP] == `PRJ_DSU_FLUSH_TYPE_WTCHPNT)) begin
							if(verbosity) $display("INST FIFO WrPtr=%d - Updating ST Bytes info=%d for GrpID=%h", inst_fifo_wr_ptr, inst_fifo_flushed[`INST_FIFO_ST_BYTES], inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL]);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] = inst_fifo_flushed[`INST_FIFO_ST_BYTES];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b1;
						inst_fifo_flushed[`INST_FIFO_GRPIDXING] = 1'b0;
						inst_fifo_flushed[`INST_FIFO_VLD]       = 1'b0;
					end
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_IA] = ia_0p2_q[63:0];
					inst_fifo_wr_ptr++;
				end		// if (inst_end_0p2_q || pre_end_0p2_q)
				
				// clear in_preamble if pre_end
				if(pre_end_0p2_q) begin
					in_preamble = 1'b0;
				end
				
			end		// if (uop_vld_0p2_q)
			
			// same for slot 1
			if(uop_vld_1p2_q) begin
				// write the gid
				//GrpIdXing Case: Clear INST_FIFO_GRPIDXING when allocating inst_fifo
				//                Set when GID is changing when inst_end is not asserted and inst_fifo GID matches previous cycle GID
				if(inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]==0) inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b0;
				if(!in_preamble && !inst_end_1p2_q && inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]
					&& ((gid_1p2_q == (gid_1p3 + 7'b0000001)) ||
					(gid_1p2_q == 7'b1000000 && gid_1p3 == 7'b0100111) ||
					(gid_1p2_q == 7'b0000000 && gid_1p3 == 7'b1100111))
					&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] != 8'b0000000
					&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] == gid_1p3) begin
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b1;
					if(verbosity) $display("GrpIdXing Case Detected!");
				end		// if(!inst_end_1p2_q )
				
				
				//This detection must be placed before inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD] assignment
				if(inst_end_1p2_q && inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]) begin
					if(inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] != gid_1p2_q[6:0])
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_SPLIT] = 1'b0;
				end
				
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD] = 1;
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMMITTED] = 1'b0;
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] = gid_1p2_q[6:0];
				
				// update ITBITS as long as it's not a preamble uop
				if(~in_preamble && ~itnoadv_1p2_q) begin		// preamble if it's a SP uop and ctl[21]==1'b1
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ITBITS] = uop_itbits_1p2_q[7:0];
				end
				else if(itnoadv_1p2_q) begin
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ITBITS] = 8'b0;
				end
				
				// update AES result count for current instruction
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_AES_CNT] += aes_dstx_cnt_1p2[1:0] + aes_dsty_cnt_1p2[1:0];
				
				// update PSR result count for current instruction
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_PSR_CNT] += resq_wrenp_1p2;
				
				// update SPW count
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_SPW_CNT] += (spr_uop_vld_1p2_q  & !uop_ctl_1p2_q[54]);		// [54]==NOP
				
				// update # of store bytes expected for current instruction
				if(ls0_uop_vld_1p2_q || ls1_uop_vld_1p2_q) begin
					if(uop_ctl_1p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_STORE) begin
						case (uop_ctl_1p2_q[`PRJ_CTL_SIZE_3])
								`PRJ_SIZE_B  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 1;
								`PRJ_SIZE_H  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 2;
								`PRJ_SIZE_3  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 3;
								`PRJ_SIZE_W  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 4;
								`PRJ_SIZE_6  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 6;
								`PRJ_SIZE_D  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 8;
								`PRJ_SIZE_12 : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 12;
								`PRJ_SIZE_16 : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 16;
							endcase		// case (uop_ctl_1p2_q[`PRJ_CTL_SIZE_3])
							//Number of Memory Op associated with this Ld/St instruction
							inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_NMOP] += 1;		//This number will indicate how many LS uops are issued before a flush or retirement
						//Store memory size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ESIZE] = {uop_ctl_1p2_q[`PRJ_CTL_ELEM_SIZE_B3],uop_ctl_1p2_q[`PRJ_CTL_ELEM_SIZE_2]};
						//Store element size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_MSIZE] = uop_ctl_1p2_q[`PRJ_CTL_SIZE_3];
						
						// see if this is STREX
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_STREX] = uop_ctl_1p2_q[`PRJ_CTL_ARM2EXT_EXCLUSIVE];
					end		// if (uop_ctl_1p2_q[`CTL_STORE])
				end
				
				// update # of load bytes expected for current instruction
				if(ls0_uop_vld_1p2_q || ls1_uop_vld_1p2_q) begin
					if(uop_ctl_1p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_LOAD

						`ifdef CORE_TESTBENCH//{
						|| (uop_ctl_1p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_MOV_ADD && !uop_ctl_1p2_q[`PRJ_CTL_NULL_CHECK])
						`endif//}

						) begin
							case (uop_ctl_1p2_q[`PRJ_CTL_SIZE_3])
								`PRJ_SIZE_B  : ld_size = 1;
								`PRJ_SIZE_H  : ld_size = 2;
								`PRJ_SIZE_3  : ld_size = 3;
								`PRJ_SIZE_W  : ld_size = 4;
								`PRJ_SIZE_6  : ld_size = 6;
								`PRJ_SIZE_D  : ld_size = 8;
								`PRJ_SIZE_12 : ld_size = 12;
								`PRJ_SIZE_16 : ld_size = 16;
							endcase		// case (uop_ctl_1p2_q[`PRJ_CTL_SIZE_3])
							//Number of Memory Op associated with this Ld/St instruction
							inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_NMOP] += 1;		//This number will indicate how many LS uops are issued before a flush or retirement
						//Store memory size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ESIZE] = {uop_ctl_1p2_q[`PRJ_CTL_ELEM_SIZE_B3],uop_ctl_1p2_q[`PRJ_CTL_ELEM_SIZE_2]};
						//Store element size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_MSIZE] = uop_ctl_1p2_q[`PRJ_CTL_SIZE_3];
						
						if (verbosity>0) $display("new load fifo entry 1p2, wr_ptr:%0d",load_fifo_wr_ptr);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LD_BYTES] += ld_size;
						
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_VLD]       = 1'b1;

						`ifdef CORE_TESTBENCH//{
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_VA_VLD]    = uop_ctl_1p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_MOV_ADD ? 1'b1 : 1'b0;
						`endif//}

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_VLD]  = dstx_tag_vld_1p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_RTAG]  = dstx_rtag_1p2_q;

						`ifdef RESULTQ_NOT_128
						load_fifo_e[load_fifo_wr_ptr][0]  = dstx_rtag_1p2_q[7];
						`endif

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_ATAG]  = dstx_atag_1p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_TYPE]  = dstx_type_1p2_q;
						//MAIA: late uop cracking - If we see both LS/SX clusters have valid uops, it's a  LS/SX late cracking case
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_VLD]  = sxj_uop_vld_1p2_q | sxk_uop_vld_1p2_q ? 1'b0 : dsty_tag_vld_1p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_RTAG]  = dsty_rtag_1p2_q;

						`ifdef RESULTQ_NOT_128
						load_fifo_e[load_fifo_wr_ptr][1]  = dsty_rtag_1p2_q[7];
						`endif

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_ATAG]  = dsty_atag_1p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_TYPE]  = dsty_type_1p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_GID_FULL]  = gid_1p2_q[6:0];
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_LD_SIZE]   = ld_size;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_INSTR]     = inst_fifo_wr_ptr;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_UNALIGNED]= 1'b0;
						load_fifo_wr_ptr++;
					end		// if (uop_ctl_1p2_q[`CTL_LOAD])
				end
				
				
				// if this is the last uop of an instruction, record ia, pop opcode, and increment inst_fifo_wr_ptr
				if((pre_end_1p2_q || inst_end_1p2_q) && ~skip_preamble) begin
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMPLETE] = 1'b1;
					if(~pre_end_1p2_q) begin
						if((verbosity>0)) $display("popping opcode 0x%08x from OPC_FIFO(%d)/FUSION_OPC_FIFO(%d) to INST_FIFO(%d)\n",opc_fifo[opc_fifo_rd_ptr],opc_fifo_rd_ptr,inst_fifo_wr_ptr,fusion_opc_fifo_rd_ptr);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_FUSEDPARENT] = fusion_opc_fifo[fusion_opc_fifo_rd_ptr];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_IFU_PCALGN_ABT_PEND] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_IFU_PCALGN_ABT_PEND];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LB_END] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_LB_END];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LB_START] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_LB_START];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_TBIT]   = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_TBIT];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ISIZE]   = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_ISIZE];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPCODE] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_OPCODE];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPC_VLD] = 1'b1;
						opc_fifo_rd_ptr++;
						fusion_opc_fifo_rd_ptr++;
					end
					//Update Store byte information from the GrpIdXing case that was flushed earlier
					else if(pre_end_1p2_q && inst_fifo_flushed[`INST_FIFO_GRPIDXING]
						&& inst_fifo_flushed[`INST_FIFO_VLD]
						&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_EN]
						&& (   inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_TYP] == `PRJ_DSU_FLUSH_TYPE_PRC_INT_DABORT
						|| inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_TYP] == `PRJ_DSU_FLUSH_TYPE_WTCHPNT)) begin
							if(verbosity) $display("INST FIFO WrPtr=%d - Updating ST Bytes info=%d for GrpID=%h", inst_fifo_wr_ptr, inst_fifo_flushed[`INST_FIFO_ST_BYTES], inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL]);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] = inst_fifo_flushed[`INST_FIFO_ST_BYTES];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b1;
						inst_fifo_flushed[`INST_FIFO_GRPIDXING] = 1'b0;
						inst_fifo_flushed[`INST_FIFO_VLD]       = 1'b0;
					end
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_IA] = ia_1p2_q[63:0];
					inst_fifo_wr_ptr++;
				end
				
				// clear in_preamble if pre_end
				if(pre_end_1p2_q) begin
					in_preamble = 1'b0;
				end
				
			end		// if (uop_vld_1p2_q)
			
			// same for slot 2
			if(uop_vld_2p2_q) begin
				// write the gid
				//GrpIdXing Case: Clear INST_FIFO_GRPIDXING when allocating inst_fifo
				//                Set when GID is changing when inst_end is not asserted and inst_fifo GID matches previous cycle GID
				if(inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]==0) inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b0;
				if(!in_preamble && !inst_end_2p2_q && inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]
					&& ((gid_2p2_q == (gid_2p3 + 7'b0000001)) ||
					(gid_2p2_q == 7'b1000000 && gid_2p3 == 7'b0100111) ||
					(gid_2p2_q == 7'b0000000 && gid_2p3 == 7'b1100111))
					&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] != 8'b0000000
					&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] == gid_2p3) begin
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b1;
					if(verbosity) $display("GrpIdXing Case Detected!");
				end		// if(!inst_end_2p2_q)
				
				
				//This detection must be placed before inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD] assignment
				if(inst_end_2p2_q && inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]) begin
					if(inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] != gid_2p2_q[6:0])
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_SPLIT] = 1'b0;
				end
				
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD] = 1;
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMMITTED] = 1'b0;
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] = gid_2p2_q[6:0];
				
				// update ITBITS as long as it's not a preamble uop
				if(~in_preamble && ~itnoadv_2p2_q) begin		// preamble if it's a SP uop and ctl[21]==1'b1
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ITBITS] = uop_itbits_2p2_q[7:0];
				end
				else if(itnoadv_2p2_q) begin
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ITBITS] = 8'b0;
				end
				
				// update AES result count for current instruction
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_AES_CNT] += aes_dstx_cnt_2p2[1:0] + aes_dsty_cnt_2p2[1:0];
				
				// update PSR result count for current instruction
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_PSR_CNT] += resq_wrenp_2p2;
				
				// update SPW count
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_SPW_CNT] += (spr_uop_vld_2p2_q  & !uop_ctl_2p2_q[54]);		// [54]==NOP
				
				// update # of store bytes expected for current instruction
				if(ls0_uop_vld_2p2_q || ls1_uop_vld_2p2_q) begin
					if(uop_ctl_2p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_STORE) begin
						case (uop_ctl_2p2_q[`PRJ_CTL_SIZE_3])
								`PRJ_SIZE_B  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 1;
								`PRJ_SIZE_H  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 2;
								`PRJ_SIZE_3  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 3;
								`PRJ_SIZE_W  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 4;
								`PRJ_SIZE_6  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 6;
								`PRJ_SIZE_D  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 8;
								`PRJ_SIZE_12 : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 12;
								`PRJ_SIZE_16 : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 16;
							endcase		// case (uop_ctl_2p2_q[`PRJ_CTL_SIZE_3])
							//Number of Memory Op associated with this Ld/St instruction
							inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_NMOP] += 1;		//This number will indicate how many LS uops are issued before a flush or retirement
						//Store memory size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ESIZE] = {uop_ctl_2p2_q[`PRJ_CTL_ELEM_SIZE_B3],uop_ctl_2p2_q[`PRJ_CTL_ELEM_SIZE_2]};
						//Store element size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_MSIZE] = uop_ctl_2p2_q[`PRJ_CTL_SIZE_3];
						
						// see if this is STREX
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_STREX] = uop_ctl_2p2_q[`PRJ_CTL_ARM2EXT_EXCLUSIVE];
					end		// if (uop_ctl_2p2_q[`CTL_STORE])
				end
				
				// update # of load bytes expected for current instruction
				if(ls0_uop_vld_2p2_q || ls1_uop_vld_2p2_q) begin
					if(uop_ctl_2p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_LOAD

						`ifdef CORE_TESTBENCH//{
						|| (uop_ctl_2p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_MOV_ADD && !uop_ctl_2p2_q[`PRJ_CTL_NULL_CHECK])
						`endif//}

						) begin
							case (uop_ctl_2p2_q[`PRJ_CTL_SIZE_3])
								`PRJ_SIZE_B  : ld_size = 1;
								`PRJ_SIZE_H  : ld_size = 2;
								`PRJ_SIZE_3  : ld_size = 3;
								`PRJ_SIZE_W  : ld_size = 4;
								`PRJ_SIZE_6  : ld_size = 6;
								`PRJ_SIZE_D  : ld_size = 8;
								`PRJ_SIZE_12 : ld_size = 12;
								`PRJ_SIZE_16 : ld_size = 16;
							endcase		// case (uop_ctl_2p2_q[`PRJ_CTL_SIZE_3])
							//Number of Memory Op associated with this Ld/St instruction
							inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_NMOP] += 1;		//This number will indicate how many LS uops are issued before a flush or retirement
						//Store memory size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ESIZE] = {uop_ctl_2p2_q[`PRJ_CTL_ELEM_SIZE_B3],uop_ctl_2p2_q[`PRJ_CTL_ELEM_SIZE_2]};
						//Store element size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_MSIZE] = uop_ctl_2p2_q[`PRJ_CTL_SIZE_3];
						
						if (verbosity>0) $display("new load fifo entry 2p2, wr_ptr:%0d",load_fifo_wr_ptr);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LD_BYTES] += ld_size;
						
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_VLD]       = 1'b1;

						`ifdef CORE_TESTBENCH//{
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_VA_VLD]    = uop_ctl_2p2_q[`PRJ_CTL_TYPE]==`PRJ_CTL_TYPE_MOV_ADD ? 1'b1 : 1'b0;
						`endif//}

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_VLD]  = dstx_tag_vld_2p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_RTAG]  = dstx_rtag_2p2_q;

						`ifdef RESULTQ_NOT_128
						load_fifo_e[load_fifo_wr_ptr][0]  = dstx_rtag_2p2_q[7];
						`endif

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_ATAG]  = dstx_atag_2p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_TYPE]  = dstx_type_2p2_q;
						//MAIA: late uop cracking - If we see both LS/SX clusters have valid uops, it's a  LS/SX late cracking case
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_VLD]  = sxj_uop_vld_2p2_q | sxk_uop_vld_2p2_q ? 1'b0 : dsty_tag_vld_2p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_RTAG]  = dsty_rtag_2p2_q;

						`ifdef RESULTQ_NOT_128
						load_fifo_e[load_fifo_wr_ptr][1]  = dsty_rtag_2p2_q[7];
						`endif

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_ATAG]  = dsty_atag_2p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_TYPE]  = dsty_type_2p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_GID_FULL]  = gid_2p2_q[6:0];
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_LD_SIZE]   = ld_size;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_INSTR]     = inst_fifo_wr_ptr;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_UNALIGNED]= 1'b0;
						load_fifo_wr_ptr++;
					end		// if (uop_ctl_2p2_q[`CTL_LOAD])
				end
				
				
				// if this is the last uop of an instruction, record ia, pop opcode, and increment inst_fifo_wr_ptr
				if((pre_end_2p2_q || inst_end_2p2_q) && ~skip_preamble) begin
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMPLETE] = 1'b1;
					if(~pre_end_2p2_q) begin
						if((verbosity>0)) $display("popping opcode 0x%08x from OPC_FIFO(%d)/FUSION_OPC_FIFO(%d) to INST_FIFO(%d)\n",opc_fifo[opc_fifo_rd_ptr],opc_fifo_rd_ptr,inst_fifo_wr_ptr,fusion_opc_fifo_rd_ptr);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_FUSEDPARENT] = fusion_opc_fifo[fusion_opc_fifo_rd_ptr];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_IFU_PCALGN_ABT_PEND] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_IFU_PCALGN_ABT_PEND];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LB_END] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_LB_END];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LB_START] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_LB_START];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_TBIT]   = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_TBIT];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ISIZE]   = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_ISIZE];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPCODE] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_OPCODE];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPC_VLD] = 1'b1;
						opc_fifo_rd_ptr++;
						fusion_opc_fifo_rd_ptr++;
					end
					//Update Store byte information from the GrpIdXing case that was flushed earlier
					else if(pre_end_2p2_q && inst_fifo_flushed[`INST_FIFO_GRPIDXING]
						&& inst_fifo_flushed[`INST_FIFO_VLD]
						&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_EN]
						&& (   inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_TYP] == `PRJ_DSU_FLUSH_TYPE_PRC_INT_DABORT
						|| inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_TYP] == `PRJ_DSU_FLUSH_TYPE_WTCHPNT)) begin
							if(verbosity) $display("INST FIFO WrPtr=%d - Updating ST Bytes info=%d for GrpID=%h", inst_fifo_wr_ptr, inst_fifo_flushed[`INST_FIFO_ST_BYTES], inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL]);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] = inst_fifo_flushed[`INST_FIFO_ST_BYTES];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b1;
						inst_fifo_flushed[`INST_FIFO_GRPIDXING] = 1'b0;
						inst_fifo_flushed[`INST_FIFO_VLD]       = 1'b0;
					end
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_IA] = ia_2p2_q[63:0];
					inst_fifo_wr_ptr++;
				end
				
				// clear in_preamble if pre_end
				if(pre_end_2p2_q) begin
					in_preamble = 1'b0;
				end
				
			end		// if (uop_vld_2p2_q)
			////---------------------- Revised by sbc@2014-03-12 11:06 BEGIN----------------------
			if(uop_vld_3p2_q) begin
				// write the gid
				//GrpIdXing Case: Clear INST_FIFO_GRPIDXING when allocating inst_fifo
				//                Set when GID is changing when inst_end is not asserted and inst_fifo GID matches previous cycle GID
				if(inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]==0) inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b0;
				if(!in_preamble && !inst_end_3p2_q && inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD]
					&& ((gid_3p2_q == (gid_3p3 + 7'b0000001)) ||
					(gid_3p2_q == 7'b1000000 && gid_3p3 == 7'b0100111) ||
					(gid_3p2_q == 7'b0000000 && gid_3p3 == 7'b1100111))
					&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] != 8'b0000000
					&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] == gid_3p3) begin
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b1;
					if(verbosity) $display("GrpIdXing Case Detected!");
				end		// if(!inst_end_3p2_q )
				
				
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_VLD] = 1;
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMMITTED] = 1'b0;
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL] = gid_3p2_q[6:0];
				
				// update ITBITS as long as it's not a preamble uop
				if(~in_preamble && ~itnoadv_3p2_q) begin		//
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ITBITS] = uop_itbits_3p2_q[7:0];
				end
				else if(itnoadv_3p2_q) begin
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ITBITS] = 8'b0;
				end
				
				// update AES result count for current instruction
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_AES_CNT] += aes_dstx_cnt_3p2[1:0] + aes_dsty_cnt_3p2[1:0];
				
				// update PSR result count for current instruction
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_PSR_CNT] += resq_wrenp_3p2;
				
				// update SPW count
				inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_SPW_CNT] += (spr_uop_vld_3p2_q & !uop_ctl_3p2_q[54]);		// [54]=NOP
				
				// update # of store bytes expected for current instruction
				if(ls0_uop_vld_3p2_q || ls1_uop_vld_3p2_q) begin
					if(uop_ctl_3p2_q[`XM_CTL_TYPE]==`XM_CTL_TYPE_STORE) begin
						case (uop_ctl_3p2_q[`XM_CTL_SIZE_3])
								`XM_SIZE_B  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 1;
								`XM_SIZE_H  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 2;
								`XM_SIZE_3  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 3;
								`XM_SIZE_W  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 4;
								`XM_SIZE_6  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 6;
								`XM_SIZE_D  : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 8;
								`XM_SIZE_12 : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 12;
								`XM_SIZE_16 : inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] += 16;
							endcase		// case (uop_ctl_3p2_q[`XM_CTL_SIZE_3])
							//Number of Memory Op associated with this Ld/St instruction
							inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_NMOP] += 1;		//This number will indicate how many LS uops are issued before a flush or retirement
						//Store memory size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ESIZE] = {uop_ctl_3p2_q[`XM_CTL_ELEM_SIZE_B3],uop_ctl_3p2_q[`XM_CTL_ELEM_SIZE_2]};
						//Store element size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_MSIZE] = uop_ctl_3p2_q[`XM_CTL_SIZE_3];
						
						// see if this is STREX
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_STREX] = uop_ctl_3p2_q[`XM_CTL_ARM2EXT_EXCLUSIVE];
					end		// if (uop_ctl_3p2_q[`CTL_STORE])
				end
				
				// update # of load bytes expected for current instruction
				// also grab tag information so we can compare later
				if(ls0_uop_vld_3p2_q || ls1_uop_vld_3p2_q) begin
					if(uop_ctl_3p2_q[`XM_CTL_TYPE]==`XM_CTL_TYPE_LOAD

						`ifdef CORE_TESTBENCH//{
						|| (uop_ctl_3p2_q[`XM_CTL_TYPE]==`XM_CTL_TYPE_MOV_ADD && !uop_ctl_3p2_q[`XM_CTL_NULL_CHECK])
						`endif//}

						) begin
							case (uop_ctl_3p2_q[`XM_CTL_SIZE_3])
								`XM_SIZE_B  : ld_size = 1;
								`XM_SIZE_H  : ld_size = 2;
								`XM_SIZE_3  : ld_size = 3;
								`XM_SIZE_W  : ld_size = 4;
								`XM_SIZE_6  : ld_size = 6;
								`XM_SIZE_D  : ld_size = 8;
								`XM_SIZE_12 : ld_size = 12;
								`XM_SIZE_16 : ld_size = 16;
							endcase		// case (uop_ctl_3p2_q[`XM_CTL_SIZE_3])
							//Number of Memory Op associated with this Ld/St instruction
							inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_NMOP] += 1;		//This number will indicate how many LS uops are issued before a flush or retirement
						//Store memory size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ESIZE] = {uop_ctl_3p2_q[`XM_CTL_ELEM_SIZE_B3],uop_ctl_3p2_q[`XM_CTL_ELEM_SIZE_2]};
						//Store element size in bytes
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_MSIZE] = uop_ctl_3p2_q[`XM_CTL_SIZE_3];
						
						if (verbosity>0) $display("new load fifo entry 0p2, wr_ptr:%0d",load_fifo_wr_ptr);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LD_BYTES] += ld_size;
						
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_VLD]       = 1'b1;

						`ifdef CORE_TESTBENCH//{
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_VA_VLD]    = uop_ctl_3p2_q[`XM_CTL_TYPE]==`XM_CTL_TYPE_MOV_ADD ? 1'b1 : 1'b0;
						`endif//}

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_VLD]  = dstx_tag_vld_3p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_RTAG]  = dstx_rtag_3p2_q;

						`ifdef RESULTQ_NOT_128
						load_fifo_e[load_fifo_wr_ptr][0]  = dstx_rtag_3p2_q[7];
						`endif

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_ATAG]  = dstx_atag_3p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTX_TYPE]  = dstx_type_3p2_q;
						//MAIA: late uop cracking - If we see both LS/SX clusters have valid uops, it's a  LS/SX late cracking case
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_VLD]  = sxj_uop_vld_3p2_q | sxk_uop_vld_3p2_q ? 1'b0 : dsty_tag_vld_3p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_RTAG]  = dsty_rtag_3p2_q;

						`ifdef RESULTQ_NOT_128
						load_fifo_e[load_fifo_wr_ptr][1]  = dsty_rtag_3p2_q[7];
						`endif

						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_ATAG]  = dsty_atag_3p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_DSTY_TYPE]  = dsty_type_3p2_q;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_GID_FULL]  = gid_3p2_q[6:0];
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_LD_SIZE]   = ld_size;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_INSTR]     = inst_fifo_wr_ptr;
						load_fifo[load_fifo_wr_ptr][`LOAD_FIFO_UNALIGNED]= 1'b0;
						load_fifo_wr_ptr++;
					end		// if (uop_ctl_3p2_q[`CTL_LOAD])
				end
				
				
				
				// if this is the last uop of an instruction, record ia, pop opcode, and increment inst_fifo_wr_ptr
				if((inst_end_3p2_q || pre_end_3p2_q) && ~skip_preamble) begin
					
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_COMPLETE] = 1'b1;
					
					if(~pre_end_3p2_q) begin
						if((verbosity>0)) $display("popping opcode 0x%08x from OPC_FIFO(%d)/FUSION_OPC_FIFO(%d) to INST_FIFO(%d)\n",opc_fifo[opc_fifo_rd_ptr],opc_fifo_rd_ptr,inst_fifo_wr_ptr,fusion_opc_fifo_rd_ptr);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_FUSEDPARENT] = fusion_opc_fifo[fusion_opc_fifo_rd_ptr];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_IFU_PCALGN_ABT_PEND] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_IFU_PCALGN_ABT_PEND];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LB_END] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_LB_END];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_LB_START] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_LB_START];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_TBIT]   = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_TBIT];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ISIZE]   = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_ISIZE];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPCODE] = opc_fifo[opc_fifo_rd_ptr][`OPC_FIFO_OPCODE];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_OPC_VLD] = 1'b1;
						opc_fifo_rd_ptr++;
						fusion_opc_fifo_rd_ptr++;
					end
					//Update Store byte information from the GrpIdXing case that was flushed earlier
					else if(pre_end_3p2_q && inst_fifo_flushed[`INST_FIFO_GRPIDXING]
						&& inst_fifo_flushed[`INST_FIFO_VLD]
						&& inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_EN]
						&& (   inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_TYP] == `XM_DSU_FLUSH_TYPE_PRC_INT_DABORT
						|| inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_EXC_TYP] == `XM_DSU_FLUSH_TYPE_WTCHPNT)) begin
							if(verbosity) $display("INST FIFO WrPtr=%d - Updating ST Bytes info=%d for GrpID=%h", inst_fifo_wr_ptr, inst_fifo_flushed[`INST_FIFO_ST_BYTES], inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GID_FULL]);
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_ST_BYTES] = inst_fifo_flushed[`INST_FIFO_ST_BYTES];
						inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_GRPIDXING] = 1'b1;
						inst_fifo_flushed[`INST_FIFO_GRPIDXING] = 1'b0;
						inst_fifo_flushed[`INST_FIFO_VLD]       = 1'b0;
					end
					inst_fifo[inst_fifo_wr_ptr][`INST_FIFO_IA] = ia_3p2_q[63:0];
					inst_fifo_wr_ptr++;
				end		// if (inst_end_3p2_q || pre_end_3p2_q)
				
				// clear in_preamble if pre_end
				if(pre_end_3p2_q) begin
					in_preamble = 1'b0;
				end
				
			end		// if (uop_vld_3p2_q)
			////---------------------- Revised by sbc@2014-03-12 11:06 END------------------------
			
			
			
			//SP p3 stage: detect WFE/WFI with pending event/interrupt
			if(sp_uop_vld_p3 && (sp_wfi_p3_q || sp_wfe_p3_q))begin
				for(i=inst_fifo_rd_ptr;i!=inst_fifo_wr_ptr;i++) begin
					if(inst_fifo[i][`INST_FIFO_GID_FULL] == sp_uop_gid_p3) begin
						inst_fifo[i][`INST_FIFO_WFEWFI_HLT] = (sp_wfi_p3_q & ~wfi_wakeup_active) | (sp_wfe_p3_q & ~wfe_wakeup_active);
						if(verbosity) $display("%d: inst_fifo[%d] setting wfe wakeup for gid:%0d to:%0b",cycle,i,inst_fifo[i][`INST_FIFO_GID_FULL], inst_fifo[i][`INST_FIFO_WFEWFI_HLT]);
					end
				end
			end
			
			// mark instructions as committed if their group's been committed
			if((verbosity>0)) $display("look for committed groups\n");
			for(i=inst_fifo_rd_ptr;i!=inst_fifo_wr_ptr;i++) begin
				if(dsu_commit_0c1 && dsu_commit_gid_0c1==inst_fifo[i][`INST_FIFO_GID_FULL])
					inst_fifo[i][`INST_FIFO_COMMITTED] = 1'b1;
				if(dsu_commit_1c1 && dsu_commit_gid_1c1==inst_fifo[i][`INST_FIFO_GID_FULL])
					inst_fifo[i][`INST_FIFO_COMMITTED] = 1'b1;
			end
			
			// do the same with the load uops
			for(i=load_fifo_rd_ptr;i!=load_fifo_wr_ptr;i++) begin
				if(dsu_commit_0c1 && dsu_commit_gid_0c1==load_fifo[i][`LOAD_FIFO_GID_FULL])
					load_fifo[i][`LOAD_FIFO_COMMITTED] = 1'b1;
				if(dsu_commit_1c1 && dsu_commit_gid_1c1==load_fifo[i][`LOAD_FIFO_GID_FULL])
					load_fifo[i][`LOAD_FIFO_COMMITTED] = 1'b1;
			end
			
			// NOTE: If you change the amount of data sent using OPC_SEND
			// then you must resize the scemi_output_pipe declaration,
			// otherwise Bad Things will happen that are hard to debug.

			//========slp=======rea====opc_send==			

			// now send any instructions that are complete and committed to the C world
			while(inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_COMMITTED] &&
				inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_COMPLETE]) begin
					if((verbosity>0)) $display("sending opcode from inst_fifo[%d]\n",inst_fifo_rd_ptr);
				// if this is the last instruction in the group, mark as such
				if ((inst_fifo[inst_fifo_rd_ptr+9'h1][`INST_FIFO_COMMITTED] &&
					inst_fifo[inst_fifo_rd_ptr+9'h1][`INST_FIFO_COMPLETE] &&
					inst_fifo[inst_fifo_rd_ptr+9'h1][`INST_FIFO_GID_FULL] !=
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_GID_FULL]))		// next instruction has different gid
					gid_end_bit = 1'b1;
				else
					gid_end_bit = 1'b0;		//If next instruction is not yet allocated, will send gid_end_bit=0 and C side will need to double check again
				
				`OPC_SEND({
				inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_GID_SPLIT],		//  1 bit: forced gid split
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_OPCODE],		//  32 bits, opcode
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_IA] ,		//  63 bits, inst addr

					`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
					32'h00000000,		//   32 bits pad
					`endif//}

					
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_FUSED_RTAG],		// 7 bit rtag info for the Fused Parent: This is to re-order the AES pkt
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_FUSEDPARENT],		// 1 bit Fused Parent indication
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_NMOP],		//  4 bit: Keep this information even the instruction got flushed <--------32bit boundary
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_ESIZE],		//  3 bit: Keep this information even the instruction got flushed
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_MSIZE],		//  3 bit: Keep this information even the instruction got flushed
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_ALGN_EXC],		//  1 bit
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_STG2_EXC],		//  1 bit
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_PWR_CYC],		//     1 bit
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_SP_ALGN_EXC],		//  1 bit
					cp15sdisable,		//     1 bit
					gid_end_bit,		//     1 bit, gid_end
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_WFEWFI_HLT],		//          1 bit, WFI/WFE is blocked by pending event/interrupt
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_GRPIDXING],		//     1 bit
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_IFU_PCALGN_ABT_PEND],		// 1 bit
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_LB_END],		//          1 bit,
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_LB_START],		//  1 bits,
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_LB_VALID],		//  1 bits,
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_ISIZE],		//  1 bits,
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_TBIT],		//  1 bits,
					
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_LD_BYTES],		//   8 bits, # ld bytes <--------32bit boundary
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_STREX],		//   1 bit, strex uop?
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_GID_FULL],		//   7 bits, gid
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_ITBITS],		//   8 bits, # itbits
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_EXC_FULL],		//   8 bits, # exception field
					
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_SPW_CNT ],		//   8 bits, # spw count <--------32bit boundary
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_AES_CNT ],		//   8 bits, # aes results
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_PSR_CNT ],		//   8 bits, # psr results
					inst_fifo[inst_fifo_rd_ptr][`INST_FIFO_ST_BYTES ],		//   8 bits, # st bytes

					`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
					32'h00000000,		//   32 bits pad
					`endif//}

					32'h00000000,		//   32 bits pad                            <--------32bit boundary
					16'h0000,		//   16 bits pad                            <--------32bit boundary
					clusterid,		//   8 bits for cluster id
					2'b00,		//   2 bits pad
					cpuid,		//   2 bits for cpuid
					`T_OPC,			     //   4 bits type
					cycle[31:0]		//  32 bits cycle number <--------32bit boundary
					});		// 192 bits = 24 bytes
			
				inst_fifo[inst_fifo_rd_ptr] = 0;
				inst_fifo_rd_ptr++;
			end
			
			// ////////////////////////////////////////////////////
			// //  Grab returning load data and VA/PA/attributes //
			// ////////////////////////////////////////////////////
			// ld_res_matched        = 1'b0;
			// ld_res_matched_entry  = 0;
			

			// `ifdef CORE_TESTBENCH//{
			// `else

			// // for sodev, grab in e4/w1 since we we know it's not cancelling because
			// // the FB was allocated
			// if (sodevnc_allocated) begin
			// 	if(unal_second_ld_e3) begin
			// 		resx_tag_vld = lsu_resx_tag_vld_w0;
			// 		resy_tag_vld = lsu_resy_tag_vld_w0;
			// 		resx_tag = lsu_resx_tag_w0;
			// 		resy_tag = lsu_resy_tag_w0;
			// 	end
			// 	else begin
			// 		resx_tag_vld = lsu_resx_tag_vld_w1;
			// 		resy_tag_vld = lsu_resy_tag_vld_w1;
			// 		resx_tag = lsu_resx_tag_w1;
			// 		resy_tag = lsu_resy_tag_w1;
			// 	end
				
			// 	if((resx_tag_vld || resy_tag_vld)) begin
			// 		for (i=load_fifo_rd_ptr; (i != load_fifo_wr_ptr) &&
			// 			load_fifo[i][`LOAD_FIFO_VLD] && !ld_res_matched; i=i+1) begin
			// 				if ((load_fifo[i][`LOAD_FIFO_DSTX_VLD] && !load_fifo[i][`LOAD_FIFO_DSTX_DVLD] && resx_tag_vld &&
			// 				(load_fifo[i][`LOAD_FIFO_DSTX_RTAG]==resx_tag[6:0]

			// 				`ifdef RESULTQ_NOT_128
			// 				&& load_fifo_e[i][0]==resx_tag[7]
			// 				`endif

			// 				)) ||
			// 				(load_fifo[i][`LOAD_FIFO_DSTY_VLD] && !load_fifo[i][`LOAD_FIFO_DSTY_DVLD] && resy_tag_vld &&
			// 				(load_fifo[i][`LOAD_FIFO_DSTY_RTAG]==resy_tag[6:0]

			// 				`ifdef RESULTQ_NOT_128
			// 				&& load_fifo_e[i][1]==resy_tag[7]
			// 				`endif

			// 				) )) begin
			// 					ld_res_matched                      = 1'b1;
							
			// 				// if an unaligned load need to grab va/pa from 1st half
			// 				// in next stage (e5/w2)
			// 				if (unal_second_ld_e4) begin
			// 					load_fifo[i][`LOAD_FIFO_UNALIGNED]= 1'b1;
			// 					load_fifo[i][`LOAD_FIFO_2ND_PA]   = {lsu_pa_ld_e4[44:4],4'b0};
			// 					load_fifo[i][`LOAD_FIFO_2ND_ATTR] = {lsu_shared_attr_ld_e4[1:0],lsu_cache_attr_ld_e4[2:0],lsu_page_attr_ld_e4[7:0]};
			// 				end else begin
			// 					load_fifo[i][`LOAD_FIFO_PA]       = lsu_pa_ld_e4;
			// 					load_fifo[i][`LOAD_FIFO_VA]       = ls_va_ld_w1;
			// 					load_fifo[i][`LOAD_FIFO_ATTR]     = {lsu_shared_attr_ld_e4[1:0],lsu_cache_attr_ld_e4[2:0],lsu_page_attr_ld_e4[7:0]};
			// 					load_fifo[i][`LOAD_FIFO_HAVE_ATTR]  = 1'b1;
			// 				end
			// 				ld_res_matched_entry                = i;
			// 			end		// if ((load_fifo[i][`LOAD_FIFO_DSTX_VLD] && !load_fifo[i][`LOAD_FIFO_DSTX_DVLD] && resx_tag_vld &&...
			// 		end		// for (i=load_fifo_rd_ptr; (i != load_fifo_wr_ptr) &&...
			// 	end		// if ((resx_tag_vld || resy_tag_vld))
			// end		// if (sodevnc_allocated)
			
			// `endif//} // CORE_TESTBENCH

			
			// // otherwise grab in e5/w2 when all data would be available and we
			// // can see cancel signal
			// if(lsu_resx_tag_vld_w2) begin
			// 	ld_resx_matched        = 1'b0;
			// end
			// else begin
			// 	ld_resx_matched        = 1'b1;
			// end
			// if(lsu_resy_tag_vld_w2) begin
			// 	ld_resy_matched        = 1'b0;
			// end
			// else begin
			// 	ld_resy_matched        = 1'b1;
			// end
			// if (lsu_resx_tag_vld_w2 || lsu_resy_tag_vld_w2

			// 	`ifdef CORE_TESTBENCH//{
			// 	|| tb_lsu_ld_j || tb_lsu_ld_k
			// 	`endif//}

			// 	) begin
			// 		// need to look through fifo for entry with matching tag since loads
			// 		// can return out-of-order

			// 		`ifdef CORE_TESTBENCH//{
			// 		if (verbosity && tb_lsu_ld_j) begin
			// 			$display("checking for va match j: tb_lsu_ld_j:%0b tb_lsu_ld_tag_j:0x%0x tb_lsu_ld_va_j:0x%0x rd:%0d wr:%0d [0].valid:%0b xm:%0b ym:%0b",
			// 			tb_lsu_ld_j,tb_lsu_ld_tag_j,tb_lsu_ld_va_j,load_fifo_rd_ptr,load_fifo_wr_ptr,load_fifo[0][`LOAD_FIFO_VLD],ld_resx_matched,ld_resy_matched);
			// 	end
			// 	if (verbosity && tb_lsu_ld_k) begin
			// 		$display("checking for va match k: tb_lsu_ld_k:%0b tb_lsu_ld_tag_k:0x%0x tb_lsu_ld_va_k:0x%0x",
			// 			tb_lsu_ld_k,tb_lsu_ld_tag_k,tb_lsu_ld_va_k);
			// 	end
			// 		`endif//}

			// 		for (i=load_fifo_rd_ptr; (i != load_fifo_wr_ptr) &&
			// 		load_fifo[i][`LOAD_FIFO_VLD] && (!ld_resx_matched || !ld_resy_matched

			// 		`ifdef CORE_TESTBENCH//{
			// 		|| tb_lsu_ld_j || tb_lsu_ld_k
			// 		`endif//}

			// 		); i=i+1) begin
			// 			if (load_fifo[i][`LOAD_FIFO_DSTX_VLD] &&
			// 			!load_fifo[i][`LOAD_FIFO_DSTX_DVLD] &&
			// 			!spo_read_par_w2 &&		//MRC PAR
			// 			lsu_resx_tag_vld_w2 &&
			// 			((load_fifo[i][`LOAD_FIFO_DSTX_RTAG]==lsu_resx_tag_w2[6:0])

			// 			`ifdef RESULTQ_NOT_128
			// 			&& (load_fifo_e[i][0]==lsu_resx_tag_w2[7])
			// 			`endif

			// 			) &&
			// 			!lsu_resx_data_cancel_w2 && !ld_resx_matched) begin
			// 				load_fifo[i][`LOAD_FIFO_RESX_DATA]  = ls_resx_data_swizzled_w2;
			// 			load_fifo[i][`LOAD_FIFO_DW]         = lsu_resx_dw_w2;
			// 			load_fifo[i][`LOAD_FIFO_SEXT]       = sext_ld_w2;
			// 			load_fifo[i][`LOAD_FIFO_CCFAIL]     = ~ls_ccpass_ld_e5;
			// 			load_fifo[i][`LOAD_FIFO_DSTX_DVLD]  = 1'b1;
			// 			ld_resx_matched                      = 1'b1;
			// 		end
			// 		if (load_fifo[i][`LOAD_FIFO_DSTY_VLD] &&
			// 			!load_fifo[i][`LOAD_FIFO_DSTY_DVLD] &&
			// 			!spo_read_par_w2 &&		//MRC PAR
			// 			lsu_resy_tag_vld_w2 &&
			// 			(load_fifo[i][`LOAD_FIFO_DSTY_RTAG]==lsu_resy_tag_w2[6:0])

			// 			`ifdef RESULTQ_NOT_128
			// 			&& (load_fifo_e[i][1]==lsu_resy_tag_w2[7])
			// 			`endif

			// 			&& !lsu_resy_data_cancel_w2 && !ld_resy_matched) begin
			// 				load_fifo[i][`LOAD_FIFO_RESY_DATA]  = ls_resy_data_swizzled_w2;
			// 			load_fifo[i][`LOAD_FIFO_DW]         = lsu_resy_dw_w2;
			// 			load_fifo[i][`LOAD_FIFO_SEXT]       = sext_ld_w2;
			// 			load_fifo[i][`LOAD_FIFO_CCFAIL]     = ~ls_ccpass_ld_e5;
			// 			load_fifo[i][`LOAD_FIFO_DSTY_DVLD]  = 1'b1;
			// 			ld_resy_matched                      = 1'b1;
			// 		end
					

					// `ifdef CORE_TESTBENCH//{
					// tb_load_tag_match_j = tb_lsu_ld_j && load_fifo[i][`LOAD_FIFO_VLD] && (load_fifo[i][`LOAD_FIFO_DSTX_RTAG] == tb_lsu_ld_tag_j);
					// tb_load_tag_match_k = tb_lsu_ld_k && load_fifo[i][`LOAD_FIFO_VLD] && (load_fifo[i][`LOAD_FIFO_DSTX_RTAG] == tb_lsu_ld_tag_k);
					
					// if (verbosity>0) $display("  fifo entry: %0d fifo_vld:%b fifo_dstx_rtag:0x%0x j_match:%0b k_match:%0b",
					// 	i,load_fifo[i][`LOAD_FIFO_VLD],load_fifo[i][`LOAD_FIFO_DSTX_RTAG],tb_load_tag_match_j,tb_load_tag_match_k);
					
					// // driven at resolve time but it doesn't need to be qualified with resolve
					// if (tb_load_tag_match_j && !load_fifo[i][`LOAD_FIFO_HAVE_ATTR]) begin
					// 	load_fifo[i][`LOAD_FIFO_HAVE_ATTR]  = 1'b1;
					// 	load_fifo[i][`LOAD_FIFO_UNALIGNED]  = 1'b0;
					// 	load_fifo[i][`LOAD_FIFO_PA]         = 45'b0;
					// 	load_fifo[i][`LOAD_FIFO_VA]         = tb_lsu_ld_va_j;
					// 	load_fifo[i][`LOAD_FIFO_VA_VLD]     = 1'b1;
					// 	load_fifo[i][`LOAD_FIFO_ATTR]       =  13'b0000000000000;
					// end
					// if (tb_load_tag_match_k && !load_fifo[i][`LOAD_FIFO_HAVE_ATTR]) begin
					// 	load_fifo[i][`LOAD_FIFO_HAVE_ATTR]  = 1'b1;
					// 	load_fifo[i][`LOAD_FIFO_UNALIGNED]  = 1'b0;
					// 	load_fifo[i][`LOAD_FIFO_PA]         = 45'b0;
					// 	load_fifo[i][`LOAD_FIFO_VA]         = tb_lsu_ld_va_k;
					// 	load_fifo[i][`LOAD_FIFO_VA_VLD]     = 1'b1;
					// 	load_fifo[i][`LOAD_FIFO_ATTR]       = 13'b0000000000000;
					// end
					
					// `else

					// // if resolved, grab pa, va, attributes
					// // if this is an unaligned load, need to grab PA/VA from 1st half
					// // in next stage (w3)
					// if (lsu_resolved_j && ld_resx_matched && !load_fifo[i][`LOAD_FIFO_HAVE_ATTR]) begin
					// 	load_fifo[i][`LOAD_FIFO_HAVE_ATTR]  = 1'b1;
					// 	if (unal_second_ld_w2) begin
					// 		load_fifo[i][`LOAD_FIFO_UNALIGNED]  = 1'b1;
					// 		load_fifo[i][`LOAD_FIFO_ATTR]       = ls_attr_ld_w3[12:0];
					// 		load_fifo[i][`LOAD_FIFO_PA]         = ls_pa_ld_w3;
					// 		load_fifo[i][`LOAD_FIFO_VA]         = ls_va_ld_w3;
							
					// 		load_fifo[i][`LOAD_FIFO_2ND_PA]     = {ls_pa_ld_w2[44:4],4'b0};
					// 		load_fifo[i][`LOAD_FIFO_2ND_ATTR]   = ls_attr_ld_w2[12:0];
					// 	end else begin
					// 		load_fifo[i][`LOAD_FIFO_PA]         = ls_pa_ld_w2;
					// 		load_fifo[i][`LOAD_FIFO_VA]         = ls_va_ld_w2;
					// 		load_fifo[i][`LOAD_FIFO_ATTR]       = ls_attr_ld_w2[12:0];
					// 	end
					// end
					// `endif//} // CORE_TESTBENCH

			// 	end		// for
			// end		// else if
			
		// 	// send load packets to C world for load uops which have data and whose
		// 	// groups have been committed (no longer speculative)
		// 	if (verbosity>0) $display("  fifo entry: %0d committed:%0d va_vld:%0d dstx_vld:%0d dstx_dvld:%0d dsty_vld:%0d dsty_dvld:%0d\n",
		// 		load_fifo_rd_ptr,load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_COMMITTED],load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_VA_VLD],load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTX_VLD],load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTX_DVLD],load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTY_VLD],load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTY_DVLD]);
		// 	while (load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_COMMITTED] &&

		// 		`ifdef CORE_TESTBENCH//{
		// 		load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_VA_VLD] &&
		// 		`endif//}

		// 		(load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTX_DVLD] || !load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTX_VLD]) &&
		// 		(load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTY_DVLD] || !load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTY_VLD])) begin
		// 			if (verbosity>0) $display("sending dstx_rtag: 0x%0x va: %016x",load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTX_RTAG],load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_VA]);
		// 		`LOD_SEND({
		// 		load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_2ND_ATTR],		// 13 bits attr
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_2ND_PA],		// 45 bits
					
		// 			5'b0,		// 5 bit pad
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_CCFAIL],		// 1 bit ccfail // 64 bit start
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_ATTR],		// 13 bits attr
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_PA],		// 45 bits PA

		// 			`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
		// 			32'h00000000,		//   32 bits pad
		// 			`endif//}

					
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTY_RTAG],		// 7 bits resy rtag
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_UNALIGNED],		// 1 bit
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTY_ATAG],		// 8 bits resy atag // 64 bit start
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DW],		//   1 bit dw bit
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTX_RTAG],		// 7 bits resx rtag
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTX_ATAG],		// 8 bits resx atag
		// 			//39'b0,                                               // 39 bit pad
					
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_VA],		// 64 bits VA // 64 bit start
					
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_RESY_DATA],		// 64 bits data // 64 bit start
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_RESX_DATA],		// 64 bits data // 64 bit start

		// 			`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
		// 			32'h00000000,		//   32 bits pad
		// 			`endif//}

					
		// 			8'h00,		//   8 bits pad                            <--------32bit boundary
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_SEXT],		// 1 bit sext // 64 bit start
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_GID_FULL],		// 7 bits gid
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_LD_SIZE],		// 8 bits size
		// 			2'b00,		// 2 bit pad
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTY_TYPE],		// 3 bits resy rtag
		// 			load_fifo[load_fifo_rd_ptr][`LOAD_FIFO_DSTX_TYPE],		// 3 bits resx type

		// 			`ifdef COMPILE_64BIT //64bit simulators need extra padding//{
		// 			64'h00000000,		//   64 bits pad
		// 			`else

		// 			32'h00000000,		//   32 bits pad                            <--------32bit boundary
		// 			`endif//}

		// 			16'h0000,		//   16 bits pad                            <--------32bit boundary
		// 			clusterid,
		// 			2'b00,		// 2 bits pad
		// 			cpuid,		// 2 bits for cpuid
		// 			`T_LOD,                                             // 4 bits type
		// 			cycle[31:0]		// 32 bit cycle count
		// 			});		// total 320 bits = 40 bytes
				
		// 		load_fifo[load_fifo_rd_ptr] = 0;
		// 		load_fifo_rd_ptr++;
		// 	end
		end
		end
		end
			end
		end
		// if((verbosity>0)) $display("end of opc_fifo/inst_fifo always\n");
		
	end		// always @ (posedge ck_gclkcr)